lpc32xx: remove surplus clock cycle in PL175 WAIT_OEN config

According to ARM PrimeCell PL175 documentation WAIT_OEN config value
is defined without any additional clocks added to the value set by a
client, the change fixes the wrong interface to WAIT_OEN config.

The change also touches a single user of LPC32xx EMC and corrects
configured "output enable delay" value on its side according to the
changed interface.

No functional change intended.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

arch/arm/include/asm/arch-lpc32xx/emc.h

@@ -70,7 +70,7 @@ struct emc_regs {
 
 /* Static Memory Delay Registers */
 #define EMC_STAT_WAITWEN(n)		(((n) - 1) & 0x0F)
-#define EMC_STAT_WAITOEN(n)		(((n) - 1) & 0x0F)
+#define EMC_STAT_WAITOEN(n)		((n) & 0x0F)
 #define EMC_STAT_WAITRD(n)		(((n) - 1) & 0x1F)
 #define EMC_STAT_WAITPAGE(n)		(((n) - 1) & 0x1F)
 #define EMC_STAT_WAITWR(n)		(((n) - 2) & 0x1F)

board/timll/devkit3250/devkit3250.c

@@ -62,7 +62,7 @@ int board_init(void)
 
 	/* Change the NOR timings to optimum value to get maximum bandwidth */
 	emc->stat[0].waitwen	= EMC_STAT_WAITWEN(1);
-	emc->stat[0].waitoen	= EMC_STAT_WAITOEN(1);
+	emc->stat[0].waitoen	= EMC_STAT_WAITOEN(0);
 	emc->stat[0].waitrd	= EMC_STAT_WAITRD(12);
 	emc->stat[0].waitpage	= EMC_STAT_WAITPAGE(12);
 	emc->stat[0].waitwr	= EMC_STAT_WAITWR(5);