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@ -117,12 +117,39 @@ static void usb_power_config(int index) |
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pll_480_ctrl_set); |
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} |
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static int wait_for_bit(u32 *reg, const u32 mask, bool set) |
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{ |
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u32 val; |
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const unsigned int timeout = 10000; |
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unsigned long start = get_timer(0); |
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while(1) { |
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val = readl(reg); |
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if (!set) |
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val = ~val; |
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if ((val & mask) == mask) |
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return 0; |
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if (get_timer(start) > timeout) |
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break; |
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udelay(1); |
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} |
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debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", |
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__func__, reg, mask, set); |
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return -ETIMEDOUT; |
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} |
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/* Return 0 : host node, <>0 : device mode */ |
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static int usb_phy_enable(int index, struct usb_ehci *ehci) |
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{ |
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void __iomem *phy_reg; |
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void __iomem *phy_ctrl; |
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void __iomem *usb_cmd; |
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int ret; |
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if (index >= ARRAY_SIZE(phy_bases)) |
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return 0; |
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@ -133,12 +160,14 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci) |
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/* Stop then Reset */ |
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clrbits_le32(usb_cmd, UCMD_RUN_STOP); |
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while (readl(usb_cmd) & UCMD_RUN_STOP) |
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; |
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ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0); |
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if (ret) |
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return ret; |
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setbits_le32(usb_cmd, UCMD_RESET); |
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while (readl(usb_cmd) & UCMD_RESET) |
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; |
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ret = wait_for_bit(usb_cmd, UCMD_RESET, 0); |
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if (ret) |
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return ret; |
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/* Reset USBPHY module */ |
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setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); |
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