This patch adds support for both the Linkstation Live (LS-CHLv2) and Linkstation Pro (LS-XHL) by Buffalo. Signed-off-by: Michael Walle <michael@walle.cc> Cc: Prafulla Wadaskar <prafulla@marvell.com>master
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#
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# Copyright (c) 2012 Michael Walle
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# Michael Walle <michael@walle.cc>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := lsxl.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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# |
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# Copyright (c) 2012 Michael Walle |
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# Michael Walle <michael@walle.cc> |
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# |
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# See file CREDITS for list of people who contributed to this |
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# project. |
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# |
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# This program is free software; you can redistribute it and/or |
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# modify it under the terms of the GNU General Public License as |
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# published by the Free Software Foundation; either version 2 of |
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# the License, or (at your option) any later version. |
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# |
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# This program is distributed in the hope that it will be useful, |
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# but WITHOUT ANY WARRANTY; without even the implied warranty of |
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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# GNU General Public License for more details. |
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# |
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# You should have received a copy of the GNU General Public License |
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# along with this program; if not, write to the Free Software |
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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# MA 02110-1301 USA |
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# |
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# Refer docs/README.kwimage for more details about how-to configure |
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# and create kirkwood boot image |
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# |
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# Boot Media configurations |
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BOOT_FROM spi |
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# SOC registers configuration using bootrom header extension |
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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# Configure RGMII-0/1 interface pad voltage to 1.8V |
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DATA 0xFFD100E0 0x1B1B1B9B |
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# L2 RAM Timing 0 |
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DATA 0xFFD20134 0xBBBBBBBB |
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# not further specified in HW manual, timing taken from original vendor port |
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# L2 RAM Timing 1 |
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DATA 0xFFD20138 0x00BBBBBB |
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# not further specified in HW manual, timing taken from original vendor port |
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# DDR Configuration register |
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DATA 0xFFD01400 0x43000618 |
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# bit13-0: 0x618, 1560 DDR2 clks refresh rate |
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# bit23-14: 0 required |
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# bit24: 1, enable exit self refresh mode on DDR access |
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# bit25: 1 required |
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# bit29-26: 0 required |
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# bit31-30: 0b01 required |
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# DDR Controller Control Low |
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DATA 0xFFD01404 0x39543000 |
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# bit3-0: 0 required |
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# bit4: 0, addr/cmd in same cycle |
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# bit5: 0, clk is driven during self refresh, we don't care for APX |
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# bit6: 0, use recommended falling edge of clk for addr/cmd |
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# bit11-7: 0 required |
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# bit12: 1 required |
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# bit13: 1 required |
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# bit14: 0, input buffer always powered up |
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# bit17-15: 0 required |
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# bit18: 1, cpu lock transaction enabled |
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# bit19: 0 required |
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# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 |
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# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM |
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# bit30-28: 3 required |
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# bit31: 0, no additional STARTBURST delay |
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# DDR Timing (Low) |
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DATA 0xFFD01408 0x3302444F |
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# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0]) |
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# bit7-4: 4, 5 cycle tRCD |
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# bit11-8: 4, 5 cyle tRP |
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# bit15-12: 4, 5 cyle tWR |
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# bit19-16: 2, 3 cyle tWTR |
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# bit20: 0, 16 cycle tRAS (tRAS[4]) |
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# bit23-21: 0 required |
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# bit27-24: 3, 4 cycle tRRD |
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# bit31-28: 3, 4 cyle tRTP |
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# DDR Timing (High) |
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DATA 0xFFD0140C 0x00000823 |
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# bit6-0: 0x23, 35 cycle tRFC |
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# bit8-7: 0, 1 cycle tR2R |
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# bit10-9: 0, 1 cyle tR2W |
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# bit12-11: 1, 2 cylce tW2W |
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# bit31-13: 0 required |
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# DDR Address Control |
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DATA 0xFFD01410 0x00000009 |
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# bit1-0: 1, Cs0width=x16 |
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# bit3-2: 2, Cs0size=512Mbit |
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# bit5-4: 0, Cs1width=nonexistent |
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# bit7-6: 0, Cs1size=nonexistent |
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# bit9-8: 0, Cs2width=nonexistent |
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# bit11-10: 0, Cs2size=nonexistent |
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# bit13-12: 0, Cs3width=nonexistent |
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# bit15-14: 0, Cs3size=nonexistent |
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# bit16: 0, Cs0AddrSel |
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# bit17: 0, Cs1AddrSel |
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# bit18: 0, Cs2AddrSel |
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# bit19: 0, Cs3AddrSel |
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# bit31-20: 0 required |
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# DDR Open Pages Control |
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DATA 0xFFD01414 0x00000000 |
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# bit0: 0, OPEn=OpenPage enabled |
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# bit31-1: 0 required |
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# DDR Operation |
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DATA 0xFFD01418 0x00000000 |
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# bit3-0: 0, Cmd=Normal SDRAM Mode |
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# bit31-4: 0 required |
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# DDR Mode |
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DATA 0xFFD0141C 0x00000652 |
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# bit2-0: 2, Burst Length (2 required) |
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# bit3: 0, Burst Type (0 required) |
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# bit6-4: 5, CAS Latency (CL) 5 |
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# bit7: 0, (Test Mode) Normal operation |
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# bit8: 0, (Reset DLL) Normal operation |
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# bit11-9: 3, Write recovery for auto-precharge (3 required) |
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# bit12: 0, Fast Active power down exit time (0 required) |
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# bit31-13: 0 required |
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# DDR Extended Mode |
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DATA 0xFFD01420 0x00000042 |
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# bit0: 0, DRAM DLL enabled |
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# bit1: 1, DRAM drive strength reduced |
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# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) |
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# bit5-3: 0 required |
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# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) |
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# bit9-7: 0 required |
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# bit10: 0, differential DQS enabled |
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# bit11: 0 required |
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# bit12: 0, DRAM output buffer enabled |
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# bit31-13: 0 required |
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# DDR Controller Control High |
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DATA 0xFFD01424 0x0000F17F |
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# bit2-0: 0x7 required |
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# bit3: 1, MBUS Burst Chop disabled |
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# bit6-4: 0x7 required |
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# bit7: 0 required (???) |
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# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz |
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# bit9: 0, no half clock cycle addition to dataout |
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# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals |
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# bit11: 0, 1/4 clock cycle skew disabled for write mesh |
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# bit15-12: 0xf required |
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# bit31-16: 0 required |
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# DDR2 ODT Read Timing (default values) |
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DATA 0xFFD01428 0x00085520 |
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# bit3-0: 0 required |
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# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal |
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# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal |
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# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal |
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# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal |
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# bit31-20: 0 required |
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# DDR2 ODT Write Timing (default values) |
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DATA 0xFFD0147C 0x00008552 |
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# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal |
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# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal |
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# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal |
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# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal |
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# bit31-16: 0 required |
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# CS[0]n Base address |
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DATA 0xFFD01500 0x00000000 |
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# at 0x0 |
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# CS[0]n Size |
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DATA 0xFFD01504 0x03FFFFF1 |
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# bit0: 1, Window enabled |
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# bit1: 0, Write Protect disabled |
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# bit3-2: 0x0, CS0 hit selected |
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# bit23-4: 0xfffff required |
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# bit31-24: 0x03, Size (i.e. 64MB) |
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# CS[1]n Size |
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DATA 0xFFD0150C 0x00000000 |
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# window disabled |
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# CS[2]n Size |
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DATA 0xFFD01514 0x00000000 |
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# window disabled |
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# CS[3]n Size |
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DATA 0xFFD0151C 0x00000000 |
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# window disabled |
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# DDR ODT Control (Low) |
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DATA 0xFFD01494 0x003C0000 |
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# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM |
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# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM |
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# bit15-8: 0 required |
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# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3 |
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# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1 |
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# bit31-24: 0 required |
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# DDR ODT Control (High) |
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DATA 0xFFD01498 0x00000000 |
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# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register |
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# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register |
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# bit31-4 0 required |
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# CPU ODT Control |
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DATA 0xFFD0149C 0x0000E80F |
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# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 |
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# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 |
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# bit9-8: 0, Internal ODT assertion is controlled by fiels |
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# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm |
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# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm |
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# bit14: 1, M_STARTBURST_IN ODT enabled |
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# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values |
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# bit20-16: 0, Pad N channel driving strength for ODT |
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# bit25-21: 0, Pad P channel driving strength for ODT |
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# bit31-26: 0 required |
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# DDR Initialization Control |
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DATA 0xFFD01480 0x00000001 |
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# bit0: 1, enable DDR init upon this register write |
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# bit31-1: 0, required |
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# End of Header extension |
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DATA 0x0 0x0 |
@ -0,0 +1,229 @@ |
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# |
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# Copyright (c) 2012 Michael Walle |
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# Michael Walle <michael@walle.cc> |
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# |
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# See file CREDITS for list of people who contributed to this |
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# project. |
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# |
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# This program is free software; you can redistribute it and/or |
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# modify it under the terms of the GNU General Public License as |
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# published by the Free Software Foundation; either version 2 of |
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# the License, or (at your option) any later version. |
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# |
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# This program is distributed in the hope that it will be useful, |
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# but WITHOUT ANY WARRANTY; without even the implied warranty of |
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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# GNU General Public License for more details. |
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# |
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# You should have received a copy of the GNU General Public License |
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# along with this program; if not, write to the Free Software |
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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# MA 02110-1301 USA |
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# |
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# Refer docs/README.kwimage for more details about how-to configure |
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# and create kirkwood boot image |
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# |
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# Boot Media configurations |
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BOOT_FROM spi |
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# SOC registers configuration using bootrom header extension |
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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# Configure RGMII-0/1 interface pad voltage to 1.8V |
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DATA 0xFFD100E0 0x1B1B9B9B |
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# L2 RAM Timing 0 |
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DATA 0xFFD20134 0xBBBBBBBB |
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# not further specified in HW manual, timing taken from original vendor port |
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# L2 RAM Timing 1 |
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DATA 0xFFD20138 0x00BBBBBB |
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# not further specified in HW manual, timing taken from original vendor port |
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# DDR Configuration register |
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DATA 0xFFD01400 0x43000618 |
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# bit13-0: 0x618, 1560 DDR2 clks refresh rate |
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# bit23-14: 0 required |
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# bit24: 1, enable exit self refresh mode on DDR access |
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# bit25: 1 required |
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# bit29-26: 0 required |
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# bit31-30: 0b01 required |
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# DDR Controller Control Low |
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DATA 0xFFD01404 0x39543010 |
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# bit3-0: 0 required |
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# bit4: 1, T2 mode, addr/cmd are driven for two cycles |
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# bit5: 0, clk is driven during self refresh, we don't care for APX |
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# bit6: 0, use recommended falling edge of clk for addr/cmd |
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# bit11-7: 0 required |
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# bit12: 1 required |
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# bit13: 1 required |
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# bit14: 0, input buffer always powered up |
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# bit17-15: 0 required |
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# bit18: 1, cpu lock transaction enabled |
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# bit19: 0 required |
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# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 |
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# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM |
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# bit30-28: 3 required |
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# bit31: 0, no additional STARTBURST delay |
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# DDR Timing (Low) |
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DATA 0xFFD01408 0x22125441 |
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# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0]) |
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# bit7-4: 4, 5 cycle tRCD |
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# bit11-8: 4, 5 cyle tRP |
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# bit15-12: 5, 6 cyle tWR |
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# bit19-16: 2, 3 cyle tWTR |
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# bit20: 1, 18 cycle tRAS (tRAS[4]) |
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# bit23-21: 0 required |
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# bit27-24: 2, 3 cycle tRRD |
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# bit31-28: 2, 3 cyle tRTP |
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# DDR Timing (High) |
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DATA 0xFFD0140C 0x00000832 |
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# bit6-0: 0x32, 50 cycle tRFC |
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# bit8-7: 0, 1 cycle tR2R |
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# bit10-9: 0, 1 cyle tR2W |
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# bit12-11: 1, 2 cylce tW2W |
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# bit31-13: 0 required |
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# DDR Address Control |
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DATA 0xFFD01410 0x0000000C |
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# bit1-0: 0, Cs0width=x8 |
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# bit3-2: 3, Cs0size=1Gbit |
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# bit5-4: 0, Cs1width=nonexistent |
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# bit7-6: 0, Cs1size=nonexistent |
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# bit9-8: 0, Cs2width=nonexistent |
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# bit11-10: 0, Cs2size=nonexistent |
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# bit13-12: 0, Cs3width=nonexistent |
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# bit15-14: 0, Cs3size=nonexistent |
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# bit16: 0, Cs0AddrSel |
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# bit17: 0, Cs1AddrSel |
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# bit18: 0, Cs2AddrSel |
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# bit19: 0, Cs3AddrSel |
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# bit31-20: 0 required |
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# DDR Open Pages Control |
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DATA 0xFFD01414 0x00000000 |
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# bit0: 0, OPEn=OpenPage enabled |
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# bit31-1: 0 required |
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# DDR Operation |
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DATA 0xFFD01418 0x00000000 |
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# bit3-0: 0, Cmd=Normal SDRAM Mode |
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# bit31-4: 0 required |
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# DDR Mode |
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DATA 0xFFD0141C 0x00000652 |
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# bit2-0: 2, Burst Length (2 required) |
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# bit3: 0, Burst Type (0 required) |
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# bit6-4: 5, CAS Latency (CL) 5 |
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# bit7: 0, (Test Mode) Normal operation |
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# bit8: 0, (Reset DLL) Normal operation |
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# bit11-9: 3, Write recovery for auto-precharge (3 required) |
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# bit12: 0, Fast Active power down exit time (0 required) |
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# bit31-13: 0 required |
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# DDR Extended Mode |
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DATA 0xFFD01420 0x00000006 |
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# bit0: 0, DRAM DLL enabled |
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# bit1: 1, DRAM drive strength reduced |
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# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination) |
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# bit5-3: 0 required |
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# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination) |
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# bit9-7: 0 required |
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# bit10: 0, differential DQS enabled |
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# bit11: 0 required |
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# bit12: 0, DRAM output buffer enabled |
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# bit31-13: 0 required |
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# DDR Controller Control High |
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DATA 0xFFD01424 0x0000F17F |
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# bit2-0: 0x7 required |
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# bit3: 1, MBUS Burst Chop disabled |
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# bit6-4: 0x7 required |
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# bit7: 0 required (???) |
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# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz |
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# bit9: 0, no half clock cycle addition to dataout |
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# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals |
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# bit11: 0, 1/4 clock cycle skew disabled for write mesh |
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# bit15-12: 0xf required |
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# bit31-16: 0 required |
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# DDR2 ODT Read Timing (default values) |
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DATA 0xFFD01428 0x00085520 |
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# bit3-0: 0 required |
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# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal |
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# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal |
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# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal |
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# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal |
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# bit31-20: 0 required |
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# DDR2 ODT Write Timing (default values) |
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DATA 0xFFD0147C 0x00008552 |
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# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal |
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# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal |
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# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal |
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# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal |
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# bit31-16: 0 required |
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# CS[0]n Base address |
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DATA 0xFFD01500 0x00000000 |
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# at 0x0 |
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# CS[0]n Size |
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DATA 0xFFD01504 0x0FFFFFF1 |
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# bit0: 1, Window enabled |
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# bit1: 0, Write Protect disabled |
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# bit3-2: 0x0, CS0 hit selected |
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# bit23-4: 0xfffff required |
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# bit31-24: 0x0f, Size (i.e. 256MB) |
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# CS[1]n Size |
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DATA 0xFFD0150C 0x00000000 |
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# window disabled |
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# CS[2]n Size |
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DATA 0xFFD01514 0x00000000 |
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# window disabled |
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# CS[3]n Size |
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DATA 0xFFD0151C 0x00000000 |
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# window disabled |
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# DDR ODT Control (Low) |
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DATA 0xFFD01494 0x00010000 |
||||
# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM |
||||
# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM |
||||
# bit15-8: 0 required |
||||
# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0 |
||||
# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM |
||||
# bit31-24: 0 required |
||||
|
||||
# DDR ODT Control (High) |
||||
DATA 0xFFD01498 0x00000000 |
||||
# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register |
||||
# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register |
||||
# bit31-4 0 required |
||||
|
||||
# CPU ODT Control |
||||
DATA 0xFFD0149C 0x0000E80F |
||||
# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 |
||||
# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 |
||||
# bit9-8: 0, Internal ODT assertion is controlled by fiels |
||||
# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm |
||||
# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm |
||||
# bit14: 1, M_STARTBURST_IN ODT enabled |
||||
# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values |
||||
# bit20-16: 0, Pad N channel driving strength for ODT |
||||
# bit25-21: 0, Pad P channel driving strength for ODT |
||||
# bit31-26: 0 required |
||||
|
||||
# DDR Initialization Control |
||||
DATA 0xFFD01480 0x00000001 |
||||
# bit0: 1, enable DDR init upon this register write |
||||
# bit31-1: 0, required |
||||
|
||||
# End of Header extension |
||||
DATA 0x0 0x0 |
@ -0,0 +1,283 @@ |
||||
/*
|
||||
* Copyright (c) 2012 Michael Walle |
||||
* Michael Walle <michael@walle.cc> |
||||
* |
||||
* Based on sheevaplug/sheevaplug.c by |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <net.h> |
||||
#include <malloc.h> |
||||
#include <netdev.h> |
||||
#include <miiphy.h> |
||||
#include <asm/arch/kirkwood.h> |
||||
#include <asm/arch/cpu.h> |
||||
#include <asm/arch/mpp.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <spi_flash.h> |
||||
|
||||
#include "lsxl.h" |
||||
|
||||
/*
|
||||
* Rescue mode |
||||
* |
||||
* Selected by holding the push button for 3 seconds, while powering on |
||||
* the device. |
||||
* |
||||
* These linkstations don't have a (populated) serial port. There is no |
||||
* way to access an (unmodified) board other than using the netconsole. If |
||||
* you want to recover from a bad environment setting or an empty environment, |
||||
* you can do this only with a working network connection. Therefore, a random |
||||
* ethernet address is generated if none is set and a DHCP request is sent. |
||||
* After a successful DHCP response is received, the network settings are |
||||
* configured and the ncip parameter is set to the serverip. Eg. for a working |
||||
* resuce mode, you should set 'next-server' to the host where the netconsole |
||||
* client is started. |
||||
* Additionally, the bootsource is set to 'rescue'. |
||||
*/ |
||||
|
||||
#ifndef CONFIG_ENV_OVERWRITE |
||||
# error "You need to set CONFIG_ENV_OVERWRITE" |
||||
#endif |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
/*
|
||||
* default gpio configuration |
||||
* There are maximum 64 gpios controlled through 2 sets of registers |
||||
* the below configuration configures mainly initial LED status |
||||
*/ |
||||
kw_config_gpio(LSXL_OE_VAL_LOW, |
||||
LSXL_OE_VAL_HIGH, |
||||
LSXL_OE_LOW, LSXL_OE_HIGH); |
||||
|
||||
/*
|
||||
* Multi-Purpose Pins Functionality configuration |
||||
* These strappings are taken from the original vendor uboot port. |
||||
*/ |
||||
u32 kwmpp_config[] = { |
||||
MPP0_SPI_SCn, |
||||
MPP1_SPI_MOSI, |
||||
MPP2_SPI_SCK, |
||||
MPP3_SPI_MISO, |
||||
MPP4_UART0_RXD, |
||||
MPP5_UART0_TXD, |
||||
MPP6_SYSRST_OUTn, |
||||
MPP7_GPO, |
||||
MPP8_GPIO, |
||||
MPP9_GPIO, |
||||
MPP10_GPO, /* HDD power */ |
||||
MPP11_GPIO, /* USB Vbus enable */ |
||||
MPP12_SD_CLK, |
||||
MPP13_SD_CMD, |
||||
MPP14_SD_D0, |
||||
MPP15_SD_D1, |
||||
MPP16_SD_D2, |
||||
MPP17_SD_D3, |
||||
MPP18_GPO, /* fan speed high */ |
||||
MPP19_GPO, /* fan speed low */ |
||||
MPP20_GE1_0, |
||||
MPP21_GE1_1, |
||||
MPP22_GE1_2, |
||||
MPP23_GE1_3, |
||||
MPP24_GE1_4, |
||||
MPP25_GE1_5, |
||||
MPP26_GE1_6, |
||||
MPP27_GE1_7, |
||||
MPP28_GPIO, |
||||
MPP29_GPIO, |
||||
MPP30_GE1_10, |
||||
MPP31_GE1_11, |
||||
MPP32_GE1_12, |
||||
MPP33_GE1_13, |
||||
MPP34_GPIO, |
||||
MPP35_GPIO, |
||||
MPP36_GPIO, /* function LED */ |
||||
MPP37_GPIO, /* alarm LED */ |
||||
MPP38_GPIO, /* info LED */ |
||||
MPP39_GPIO, /* power LED */ |
||||
MPP40_GPIO, /* fan alarm */ |
||||
MPP41_GPIO, /* funtion button */ |
||||
MPP42_GPIO, /* power switch */ |
||||
MPP43_GPIO, /* power auto switch */ |
||||
MPP44_GPIO, |
||||
MPP45_GPIO, |
||||
MPP46_GPIO, |
||||
MPP47_GPIO, |
||||
MPP48_GPIO, /* function red LED */ |
||||
MPP49_GPIO, |
||||
0 |
||||
}; |
||||
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#define LED_OFF 0 |
||||
#define LED_ALARM_ON 1 |
||||
#define LED_ALARM_BLINKING 2 |
||||
#define LED_POWER_ON 3 |
||||
#define LED_POWER_BLINKING 4 |
||||
#define LED_INFO_ON 5 |
||||
#define LED_INFO_BLINKING 6 |
||||
|
||||
static void __set_led(int blink_alarm, int blink_info, int blink_power, |
||||
int value_alarm, int value_info, int value_power) |
||||
{ |
||||
kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm); |
||||
kw_gpio_set_blink(GPIO_INFO_LED, blink_info); |
||||
kw_gpio_set_blink(GPIO_POWER_LED, blink_power); |
||||
kw_gpio_set_value(GPIO_ALARM_LED, value_alarm); |
||||
kw_gpio_set_value(GPIO_INFO_LED, value_info); |
||||
kw_gpio_set_value(GPIO_POWER_LED, value_power); |
||||
} |
||||
|
||||
static void set_led(int state) |
||||
{ |
||||
switch (state) { |
||||
case LED_OFF: |
||||
__set_led(0, 0, 0, 0, 0, 0); |
||||
break; |
||||
case LED_ALARM_ON: |
||||
__set_led(0, 0, 0, 0, 1, 1); |
||||
break; |
||||
case LED_ALARM_BLINKING: |
||||
__set_led(1, 0, 0, 1, 1, 1); |
||||
break; |
||||
case LED_INFO_ON: |
||||
__set_led(0, 0, 0, 1, 0, 1); |
||||
break; |
||||
case LED_INFO_BLINKING: |
||||
__set_led(0, 1, 0, 1, 1, 1); |
||||
break; |
||||
case LED_POWER_ON: |
||||
__set_led(0, 0, 0, 1, 1, 0); |
||||
break; |
||||
case LED_POWER_BLINKING: |
||||
__set_led(0, 0, 1, 1, 1, 1); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; |
||||
|
||||
set_led(LED_POWER_BLINKING); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_MISC_INIT_R |
||||
void check_enetaddr(void) |
||||
{ |
||||
uchar enetaddr[6]; |
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { |
||||
/* signal unset/invalid ethaddr to user */ |
||||
set_led(LED_INFO_BLINKING); |
||||
} |
||||
} |
||||
|
||||
static void erase_environment(void) |
||||
{ |
||||
struct spi_flash *flash; |
||||
|
||||
printf("Erasing environment..\n"); |
||||
flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); |
||||
if (!flash) { |
||||
printf("Erasing flash failed\n"); |
||||
return; |
||||
} |
||||
|
||||
spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE); |
||||
spi_flash_free(flash); |
||||
do_reset(NULL, 0, 0, NULL); |
||||
} |
||||
|
||||
static void rescue_mode(void) |
||||
{ |
||||
uchar enetaddr[6]; |
||||
|
||||
printf("Entering rescue mode..\n"); |
||||
#ifdef CONFIG_RANDOM_MACADDR |
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { |
||||
eth_random_enetaddr(enetaddr); |
||||
if (eth_setenv_enetaddr("ethaddr", enetaddr)) { |
||||
printf("Failed to set ethernet address\n"); |
||||
set_led(LED_ALARM_BLINKING); |
||||
return; |
||||
} |
||||
} |
||||
#endif |
||||
setenv("bootsource", "rescue"); |
||||
} |
||||
|
||||
static void check_push_button(void) |
||||
{ |
||||
int i = 0; |
||||
|
||||
while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) { |
||||
udelay(100000); |
||||
i++; |
||||
|
||||
if (i == 10) |
||||
set_led(LED_INFO_ON); |
||||
|
||||
if (i >= 100) { |
||||
set_led(LED_INFO_BLINKING); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if (i >= 100) |
||||
erase_environment(); |
||||
else if (i >= 10) |
||||
rescue_mode(); |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
check_enetaddr(); |
||||
check_push_button(); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS |
||||
void show_boot_progress(int progress) |
||||
{ |
||||
if (progress > 0) |
||||
return; |
||||
|
||||
/* this is not an error, eg. bootp with autoload=no will trigger this */ |
||||
if (progress == -BOOTSTAGE_ID_NET_LOADED) |
||||
return; |
||||
|
||||
set_led(LED_ALARM_BLINKING); |
||||
} |
||||
#endif |
@ -0,0 +1,75 @@ |
||||
/*
|
||||
* Copyright (c) 2012 Michael Walle |
||||
* Michael Walle <michael@walle.cc> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#ifndef __LSXL_H |
||||
#define __LSXL_H |
||||
|
||||
#define GPIO_HDD_POWER 10 |
||||
#define GPIO_USB_VBUS 11 |
||||
#define GPIO_FAN_HIGH 18 |
||||
#define GPIO_FAN_LOW 19 |
||||
#define GPIO_FUNC_LED 36 |
||||
#define GPIO_ALARM_LED 37 |
||||
#define GPIO_INFO_LED 38 |
||||
#define GPIO_POWER_LED 39 |
||||
#define GPIO_FAN_LOCK 40 |
||||
#define GPIO_FUNC_BUTTON 41 |
||||
#define GPIO_POWER_SWITCH 42 |
||||
#define GPIO_POWER_AUTO_SWITCH 43 |
||||
#define GPIO_FUNC_RED_LED 48 |
||||
|
||||
#define _BIT(x) (1<<(x)) |
||||
|
||||
#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER) \ |
||||
| _BIT(GPIO_USB_VBUS) \
|
||||
| _BIT(GPIO_FAN_HIGH) \
|
||||
| _BIT(GPIO_FAN_LOW))) |
||||
|
||||
#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32) \ |
||||
| _BIT(GPIO_ALARM_LED - 32) \
|
||||
| _BIT(GPIO_INFO_LED - 32) \
|
||||
| _BIT(GPIO_POWER_LED - 32) \
|
||||
| _BIT(GPIO_FUNC_RED_LED - 32))) |
||||
|
||||
#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER) \ |
||||
| _BIT(GPIO_USB_VBUS)) |
||||
|
||||
#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ |
||||
| _BIT(GPIO_ALARM_LED - 32) \
|
||||
| _BIT(GPIO_INFO_LED - 32) \
|
||||
| _BIT(GPIO_POWER_LED - 32) \
|
||||
| _BIT(GPIO_FUNC_RED_LED - 32)) |
||||
|
||||
#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH) \ |
||||
| _BIT(GPIO_FAN_LOW)) |
||||
|
||||
#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ |
||||
| _BIT(GPIO_ALARM_LED - 32) \
|
||||
| _BIT(GPIO_INFO_LED - 32) \
|
||||
| _BIT(GPIO_POWER_LED - 32) \
|
||||
| _BIT(GPIO_FUNC_BUTTON - 32) \
|
||||
| _BIT(GPIO_POWER_SWITCH - 32) \
|
||||
| _BIT(GPIO_POWER_AUTO_SWITCH - 32) \
|
||||
| _BIT(GPIO_FUNC_RED_LED - 32)) |
||||
|
||||
#endif /* __LSXL_H */ |
@ -0,0 +1,182 @@ |
||||
/*
|
||||
* Copyright (c) 2012 Michael Walle |
||||
* Michael Walle <michael@walle.cc> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#ifndef _CONFIG_LSXL_H |
||||
#define _CONFIG_LSXL_H |
||||
|
||||
/*
|
||||
* Version number information |
||||
*/ |
||||
#if defined(CONFIG_LSCHLV2) |
||||
#define CONFIG_IDENT_STRING " LS-CHLv2" |
||||
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg |
||||
#define CONFIG_MACH_TYPE 3006 |
||||
#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */ |
||||
#elif defined(CONFIG_LSXHL) |
||||
#define CONFIG_IDENT_STRING " LS-XHL" |
||||
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg |
||||
#define CONFIG_MACH_TYPE 2663 |
||||
/* CONFIG_SYS_TCLK is 200000000 by default */ |
||||
#else |
||||
#error "unknown board" |
||||
#endif |
||||
|
||||
/*
|
||||
* General configuration options |
||||
*/ |
||||
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ |
||||
#define CONFIG_KIRKWOOD /* SOC Family Name */ |
||||
#define CONFIG_KW88F6281 /* SOC Name */ |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_SHOW_BOOT_PROGRESS |
||||
|
||||
#define CONFIG_RANDOM_MACADDR |
||||
#define CONFIG_KIRKWOOD_GPIO |
||||
#define CONFIG_OF_LIBFDT |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET |
||||
|
||||
/*
|
||||
* Enable u-boot API for standalone programs. |
||||
*/ |
||||
#define CONFIG_API |
||||
|
||||
/*
|
||||
* Commands configuration |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_CMD_SPI |
||||
#define CONFIG_CMD_USB |
||||
|
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_EFI_PARTITION |
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them |
||||
* to enable certain macros |
||||
*/ |
||||
#include "mv-common.h" |
||||
|
||||
/* ST M25P40 */ |
||||
#undef CONFIG_SPI_FLASH_MACRONIX |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#undef CONFIG_ENV_SPI_MAX_HZ |
||||
#define CONFIG_ENV_SPI_MAX_HZ 25000000 |
||||
#undef CONFIG_SF_DEFAULT_SPEED |
||||
#define CONFIG_SF_DEFAULT_SPEED 25000000 |
||||
|
||||
|
||||
#undef CONFIG_SYS_PROMPT |
||||
#define CONFIG_SYS_PROMPT "=> " |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/*
|
||||
* Environment variables configurations |
||||
*/ |
||||
#ifdef CONFIG_SPI_FLASH |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 8 |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */ |
||||
#else |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#endif |
||||
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* 64k */ |
||||
#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ |
||||
|
||||
/*
|
||||
* Default environment variables |
||||
*/ |
||||
#define CONFIG_LOADADDR 0x00800000 |
||||
#define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}" |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2" |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"bootsource=hdd\0" \
|
||||
"hdpart=0:1\0" \
|
||||
"bootcmd_net=bootp 0x00100000 uImage " \
|
||||
"&& tftpboot 0x00800000 uInitrd " \
|
||||
"&& bootm 0x00100000 0x00800000\0" \
|
||||
"bootcmd_hdd=ide reset " \
|
||||
"&& ext2load ide ${hdpart} 0x00100000 /uImage " \
|
||||
"&& ext2load ide ${hdpart} 0x00800000 /uInitrd " \
|
||||
"&& bootm 0x00100000 0x00800000\0" \
|
||||
"bootcmd_usb=usb start " \
|
||||
"&& fatload usb 0:1 0x00100000 /uImage " \
|
||||
"&& fatload usb 0:1 0x00800000 /uInitrd " \
|
||||
"&& bootm 0x00100000 0x00800000\0" \
|
||||
"bootcmd_rescue=run config_nc_dhcp; run nc\0" \
|
||||
"eraseenv=sf probe 0 " \
|
||||
"&& sf erase " MK_STR(CONFIG_ENV_OFFSET) \
|
||||
" +" MK_STR(CONFIG_ENV_SIZE) "\0" \
|
||||
"config_nc_dhcp=setenv autoload_old ${autoload}; " \
|
||||
"setenv autoload no " \
|
||||
"&& bootp " \
|
||||
"&& setenv ncip ${serverip} " \
|
||||
"&& setenv autoload ${autoload_old}; " \
|
||||
"setenv autoload_old\0" \
|
||||
"standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \
|
||||
"setenv ncip; setenv gatewayip; setenv ethact; " \
|
||||
"setenv bootfile; setenv dnsip; " \
|
||||
"setenv bootsource hdd; run ser\0" \
|
||||
"restore_env=run standard_env; saveenv; reset\0" \
|
||||
"ser=setenv stdin serial; setenv stdout serial; " \
|
||||
"setenv stderr serial\0" \
|
||||
"nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \
|
||||
"stdin=serial\0" \
|
||||
"stdout=serial\0" \
|
||||
"stderr=serial\0" |
||||
|
||||
/*
|
||||
* Ethernet Driver configuration |
||||
*/ |
||||
#ifdef CONFIG_CMD_NET |
||||
#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */ |
||||
#define CONFIG_PHY_BASE_ADR 7 |
||||
#undef CONFIG_RESET_PHY_R |
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
#ifdef CONFIG_CMD_IDE |
||||
#undef CONFIG_IDE_LED |
||||
#undef CONFIG_SYS_IDE_MAXBUS |
||||
#define CONFIG_SYS_IDE_MAXBUS 1 |
||||
#undef CONFIG_SYS_IDE_MAXDEVICE |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 |
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET |
||||
#endif |
||||
|
||||
#endif /* _CONFIG_LSXL_H */ |
Loading…
Reference in new issue