Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>master
Daniel Hellstrom
15 years ago
committed by
Francois Retief
parent
cff009ed6f
commit
f2879f5952
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/* GRLIB APBUART definitions
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* |
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* (C) Copyright 2010, 2015 |
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* Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __GRLIB_APBUART_H__ |
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#define __GRLIB_APBUART_H__ |
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/* APBUART Register map */ |
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typedef struct { |
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volatile unsigned int data; |
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volatile unsigned int status; |
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volatile unsigned int ctrl; |
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volatile unsigned int scaler; |
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} ambapp_dev_apbuart; |
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/*
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* The following defines the bits in the LEON UART Status Registers. |
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*/ |
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#define APBUART_STATUS_DR 0x00000001 /* Data Ready */ |
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#define APBUART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ |
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#define APBUART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ |
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#define APBUART_STATUS_BR 0x00000008 /* Break Error */ |
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#define APBUART_STATUS_OE 0x00000010 /* RX Overrun Error */ |
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#define APBUART_STATUS_PE 0x00000020 /* RX Parity Error */ |
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#define APBUART_STATUS_FE 0x00000040 /* RX Framing Error */ |
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#define APBUART_STATUS_ERR 0x00000078 /* Error Mask */ |
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/*
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* The following defines the bits in the LEON UART Ctrl Registers. |
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*/ |
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#define APBUART_CTRL_RE 0x00000001 /* Receiver enable */ |
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#define APBUART_CTRL_TE 0x00000002 /* Transmitter enable */ |
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#define APBUART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ |
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#define APBUART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ |
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#define APBUART_CTRL_PS 0x00000010 /* Parity select */ |
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#define APBUART_CTRL_PE 0x00000020 /* Parity enable */ |
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#define APBUART_CTRL_FL 0x00000040 /* Flow control enable */ |
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#define APBUART_CTRL_LB 0x00000080 /* Loop Back enable */ |
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#define APBUART_CTRL_DBG (1<<11) /* Debug Bit used by GRMON */ |
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#endif |
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/* GRLIB GPTIMER (General Purpose Timer) definitions
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* |
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* (C) Copyright 2010, 2015 |
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* Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __GRLIB_GPTIMER_H__ |
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#define __GRLIB_GPTIMER_H__ |
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typedef struct { |
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volatile unsigned int val; |
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volatile unsigned int rld; |
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volatile unsigned int ctrl; |
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volatile unsigned int unused; |
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} ambapp_dev_gptimer_element; |
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#define GPTIMER_CTRL_EN 0x1 /* Timer enable */ |
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#define GPTIMER_CTRL_RS 0x2 /* Timer reStart */ |
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#define GPTIMER_CTRL_LD 0x4 /* Timer reLoad */ |
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#define GPTIMER_CTRL_IE 0x8 /* interrupt enable */ |
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#define GPTIMER_CTRL_IP 0x10 /* interrupt flag/pending */ |
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#define GPTIMER_CTRL_CH 0x20 /* Chain with previous timer */ |
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typedef struct { |
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volatile unsigned int scalar; |
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volatile unsigned int scalar_reload; |
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volatile unsigned int config; |
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volatile unsigned int unused; |
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volatile ambapp_dev_gptimer_element e[8]; |
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} ambapp_dev_gptimer; |
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#endif |
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/* Gaisler.com GRETH 10/100/1000 Ethernet MAC definitions
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* |
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* (C) Copyright 2010, 2015 |
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* Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __GRLIB_GRETH_H__ |
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#define __GRLIB_GRETH_H__ |
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#define GRETH_FD 0x10 |
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#define GRETH_RESET 0x40 |
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#define GRETH_MII_BUSY 0x8 |
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#define GRETH_MII_NVALID 0x10 |
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/* MII registers */ |
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#define GRETH_MII_EXTADV_1000FD 0x00000200 |
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#define GRETH_MII_EXTADV_1000HD 0x00000100 |
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#define GRETH_MII_EXTPRT_1000FD 0x00000800 |
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#define GRETH_MII_EXTPRT_1000HD 0x00000400 |
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#define GRETH_MII_100T4 0x00000200 |
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#define GRETH_MII_100TXFD 0x00000100 |
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#define GRETH_MII_100TXHD 0x00000080 |
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#define GRETH_MII_10FD 0x00000040 |
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#define GRETH_MII_10HD 0x00000020 |
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#define GRETH_BD_EN 0x800 |
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#define GRETH_BD_WR 0x1000 |
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#define GRETH_BD_IE 0x2000 |
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#define GRETH_BD_LEN 0x7FF |
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#define GRETH_TXEN 0x1 |
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#define GRETH_INT_TX 0x8 |
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#define GRETH_TXI 0x4 |
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#define GRETH_TXBD_STATUS 0x0001C000 |
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#define GRETH_TXBD_MORE 0x20000 |
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#define GRETH_TXBD_IPCS 0x40000 |
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#define GRETH_TXBD_TCPCS 0x80000 |
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#define GRETH_TXBD_UDPCS 0x100000 |
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#define GRETH_TXBD_ERR_LC 0x10000 |
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#define GRETH_TXBD_ERR_UE 0x4000 |
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#define GRETH_TXBD_ERR_AL 0x8000 |
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#define GRETH_TXBD_NUM 128 |
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#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1) |
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#define GRETH_TX_BUF_SIZE 2048 |
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#define GRETH_INT_RX 0x4 |
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#define GRETH_RXEN 0x2 |
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#define GRETH_RXI 0x8 |
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#define GRETH_RXBD_STATUS 0xFFFFC000 |
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#define GRETH_RXBD_ERR_AE 0x4000 |
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#define GRETH_RXBD_ERR_FT 0x8000 |
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#define GRETH_RXBD_ERR_CRC 0x10000 |
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#define GRETH_RXBD_ERR_OE 0x20000 |
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#define GRETH_RXBD_ERR_LE 0x40000 |
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#define GRETH_RXBD_IP_DEC 0x80000 |
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#define GRETH_RXBD_IP_CSERR 0x100000 |
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#define GRETH_RXBD_UDP_DEC 0x200000 |
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#define GRETH_RXBD_UDP_CSERR 0x400000 |
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#define GRETH_RXBD_TCP_DEC 0x800000 |
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#define GRETH_RXBD_TCP_CSERR 0x1000000 |
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#define GRETH_RXBD_NUM 128 |
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#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1) |
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#define GRETH_RX_BUF_SIZE 2048 |
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/* Ethernet configuration registers */ |
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typedef struct _greth_regs { |
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volatile unsigned int control; |
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volatile unsigned int status; |
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volatile unsigned int esa_msb; |
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volatile unsigned int esa_lsb; |
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volatile unsigned int mdio; |
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volatile unsigned int tx_desc_p; |
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volatile unsigned int rx_desc_p; |
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volatile unsigned int edcl_ip; |
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} greth_regs; |
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/* Ethernet buffer descriptor */ |
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typedef struct _greth_bd { |
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volatile unsigned int stat; |
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unsigned int addr; /* Buffer address not changed by HW */ |
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} greth_bd; |
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#endif |
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/* GRLIB IRQMP (IRQ Multi-processor controller) definitions
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* |
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* (C) Copyright 2010, 2015 |
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* Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __GRLIB_IRQMP_H__ |
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#define __GRLIB_IRQMP_H__ |
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typedef struct { |
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volatile unsigned int ilevel; |
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volatile unsigned int ipend; |
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volatile unsigned int iforce; |
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volatile unsigned int iclear; |
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volatile unsigned int mstatus; |
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volatile unsigned int notused[11]; |
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volatile unsigned int cpu_mask[16]; |
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volatile unsigned int cpu_force[16]; |
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} ambapp_dev_irqmp; |
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#endif |
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