@ -191,15 +191,15 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
. sdram_config_init = 0x61862B32 ,
. sdram_config = 0x61862B32 ,
. sdram_config2 = 0x08000000 ,
. ref_ctrl = 0x0000493E ,
. ref_ctrl = 0x0000514C ,
. ref_ctrl_final = 0x0000144A ,
. sdram_tim1 = 0xD113781C ,
. sdram_tim2 = 0x308F7FE3 ,
. sdram_tim3 = 0x0 09F86A8 ,
. sdram_tim2 = 0x305A7FDA ,
. sdram_tim3 = 0x4 09F86A8 ,
. read_idle_ctrl = 0x00050000 ,
. zq_config = 0x0 007190B ,
. zq_config = 0x5 007190B ,
. temp_alert_config = 0x00000000 ,
. emif_ddr_phy_ctlr_1_init = 0x0E 24400D ,
. emif_ddr_phy_ctlr_1_init = 0x00 24400D ,
. emif_ddr_phy_ctlr_1 = 0x0E24400D ,
. emif_ddr_ext_phy_ctrl_1 = 0x10040100 ,
. emif_ddr_ext_phy_ctrl_2 = 0x00A400A4 ,
@ -207,7 +207,7 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
. emif_ddr_ext_phy_ctrl_4 = 0x00B000B0 ,
. emif_ddr_ext_phy_ctrl_5 = 0x00B000B0 ,
. emif_rd_wr_lvl_rmp_win = 0x00000000 ,
. emif_rd_wr_lvl_rmp_ctl = 0x0 0000000 ,
. emif_rd_wr_lvl_rmp_ctl = 0x8 0000000 ,
. emif_rd_wr_lvl_ctl = 0x00000000 ,
. emif_rd_wr_exec_thresh = 0x00000305
} ;
@ -533,6 +533,11 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
0x0 ,
0x0 ,
0x0 ,
0x0 ,
0x0 ,
0x0 ,
0x0 ,
0x0 ,
0x0
} ;