commit
f38536f913
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/*
|
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* (C) Copyright 2010-2011 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include "ap20.h" |
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#include <asm/io.h> |
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#include <asm/arch/tegra2.h> |
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#include <asm/arch/clk_rst.h> |
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#include <asm/arch/pmc.h> |
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#include <asm/arch/pinmux.h> |
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#include <asm/arch/scu.h> |
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#include <common.h> |
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u32 s_first_boot = 1; |
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void init_pllx(void) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 reg; |
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/* If PLLX is already enabled, just return */ |
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reg = readl(&clkrst->crc_pllx_base); |
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if (reg & PLL_ENABLE) |
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return; |
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/* Set PLLX_MISC */ |
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reg = CPCON; /* CPCON[11:8] = 0001 */ |
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writel(reg, &clkrst->crc_pllx_misc); |
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|
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/* Use 12MHz clock here */ |
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reg = (PLL_BYPASS | PLL_DIVM); |
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reg |= (1000 << 8); /* DIVN = 0x3E8 */ |
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writel(reg, &clkrst->crc_pllx_base); |
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reg |= PLL_ENABLE; |
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writel(reg, &clkrst->crc_pllx_base); |
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reg &= ~PLL_BYPASS; |
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writel(reg, &clkrst->crc_pllx_base); |
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} |
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static void enable_cpu_clock(int enable) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 reg, clk; |
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/*
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* NOTE: |
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* Regardless of whether the request is to enable or disable the CPU |
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* clock, every processor in the CPU complex except the master (CPU 0) |
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* will have it's clock stopped because the AVP only talks to the |
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* master. The AVP does not know (nor does it need to know) that there |
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* are multiple processors in the CPU complex. |
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*/ |
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if (enable) { |
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/* Initialize PLLX */ |
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init_pllx(); |
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|
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/* Wait until all clocks are stable */ |
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udelay(PLL_STABILIZATION_DELAY); |
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writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); |
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writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); |
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} |
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|
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/* Fetch the register containing the main CPU complex clock enable */ |
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reg = readl(&clkrst->crc_clk_out_enb_l); |
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reg |= CLK_ENB_CPU; |
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/*
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* Read the register containing the individual CPU clock enables and |
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* always stop the clock to CPU 1. |
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*/ |
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clk = readl(&clkrst->crc_clk_cpu_cmplx); |
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clk |= CPU1_CLK_STP; |
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if (enable) { |
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/* Unstop the CPU clock */ |
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clk &= ~CPU0_CLK_STP; |
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} else { |
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/* Stop the CPU clock */ |
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clk |= CPU0_CLK_STP; |
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} |
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writel(clk, &clkrst->crc_clk_cpu_cmplx); |
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writel(reg, &clkrst->crc_clk_out_enb_l); |
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} |
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static int is_cpu_powered(void) |
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{ |
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; |
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} |
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static void remove_cpu_io_clamps(void) |
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{ |
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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u32 reg; |
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/* Remove the clamps on the CPU I/O signals */ |
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reg = readl(&pmc->pmc_remove_clamping); |
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reg |= CPU_CLMP; |
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writel(reg, &pmc->pmc_remove_clamping); |
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/* Give I/O signals time to stabilize */ |
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udelay(IO_STABILIZATION_DELAY); |
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} |
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static void powerup_cpu(void) |
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{ |
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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u32 reg; |
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int timeout = IO_STABILIZATION_DELAY; |
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if (!is_cpu_powered()) { |
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/* Toggle the CPU power state (OFF -> ON) */ |
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reg = readl(&pmc->pmc_pwrgate_toggle); |
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reg &= PARTID_CP; |
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reg |= START_CP; |
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writel(reg, &pmc->pmc_pwrgate_toggle); |
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|
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/* Wait for the power to come up */ |
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while (!is_cpu_powered()) { |
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if (timeout-- == 0) |
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printf("CPU failed to power up!\n"); |
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else |
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udelay(10); |
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} |
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|
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/*
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* Remove the I/O clamps from CPU power partition. |
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* Recommended only on a Warm boot, if the CPU partition gets |
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* power gated. Shouldn't cause any harm when called after a |
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* cold boot according to HW, probably just redundant. |
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*/ |
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remove_cpu_io_clamps(); |
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} |
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} |
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static void enable_cpu_power_rail(void) |
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{ |
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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u32 reg; |
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reg = readl(&pmc->pmc_cntrl); |
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reg |= CPUPWRREQ_OE; |
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writel(reg, &pmc->pmc_cntrl); |
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/*
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* The TI PMU65861C needs a 3.75ms delay between enabling |
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* the power rail and enabling the CPU clock. This delay |
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* between SM1EN and SM1 is for switching time + the ramp |
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* up of the voltage to the CPU (VDD_CPU from PMU). |
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*/ |
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udelay(3750); |
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} |
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static void reset_A9_cpu(int reset) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 reg, cpu; |
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/*
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* NOTE: Regardless of whether the request is to hold the CPU in reset |
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* or take it out of reset, every processor in the CPU complex |
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* except the master (CPU 0) will be held in reset because the |
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* AVP only talks to the master. The AVP does not know that there |
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* are multiple processors in the CPU complex. |
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*/ |
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/* Hold CPU 1 in reset */ |
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cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1; |
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writel(cpu, &clkrst->crc_cpu_cmplx_set); |
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reg = readl(&clkrst->crc_rst_dev_l); |
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if (reset) { |
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/* Now place CPU0 into reset */ |
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cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0; |
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writel(cpu, &clkrst->crc_cpu_cmplx_set); |
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/* Enable master CPU reset */ |
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reg |= SWR_CPU_RST; |
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} else { |
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/* Take CPU0 out of reset */ |
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cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0; |
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writel(cpu, &clkrst->crc_cpu_cmplx_clr); |
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/* Disable master CPU reset */ |
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reg &= ~SWR_CPU_RST; |
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} |
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writel(reg, &clkrst->crc_rst_dev_l); |
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} |
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static void clock_enable_coresight(int enable) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 rst, clk, src; |
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rst = readl(&clkrst->crc_rst_dev_u); |
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clk = readl(&clkrst->crc_clk_out_enb_u); |
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if (enable) { |
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rst &= ~SWR_CSITE_RST; |
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clk |= CLK_ENB_CSITE; |
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} else { |
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rst |= SWR_CSITE_RST; |
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clk &= ~CLK_ENB_CSITE; |
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} |
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writel(clk, &clkrst->crc_clk_out_enb_u); |
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writel(rst, &clkrst->crc_rst_dev_u); |
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if (enable) { |
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/*
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* Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by |
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* 1.5, giving an effective frequency of 144MHz. |
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* Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor |
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* (bits 7:0), so 00000001b == 1.5 (n+1 + .5) |
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*/ |
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src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); |
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writel(src, &clkrst->crc_clk_src_csite); |
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/* Unlock the CPU CoreSight interfaces */ |
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rst = 0xC5ACCE55; |
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writel(rst, CSITE_CPU_DBG0_LAR); |
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writel(rst, CSITE_CPU_DBG1_LAR); |
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} |
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} |
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void start_cpu(u32 reset_vector) |
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{ |
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/* Enable VDD_CPU */ |
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enable_cpu_power_rail(); |
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/* Hold the CPUs in reset */ |
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reset_A9_cpu(1); |
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/* Disable the CPU clock */ |
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enable_cpu_clock(0); |
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/* Enable CoreSight */ |
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clock_enable_coresight(1); |
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/*
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* Set the entry point for CPU execution from reset, |
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* if it's a non-zero value. |
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*/ |
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if (reset_vector) |
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writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); |
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/* Enable the CPU clock */ |
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enable_cpu_clock(1); |
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/* If the CPU doesn't already have power, power it up */ |
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powerup_cpu(); |
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/* Take the CPU out of reset */ |
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reset_A9_cpu(0); |
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} |
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void halt_avp(void) |
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{ |
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for (;;) { |
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writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
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| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)), |
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FLOW_CTLR_HALT_COP_EVENTS); |
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} |
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} |
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void enable_scu(void) |
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{ |
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struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; |
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u32 reg; |
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/* If SCU already setup/enabled, return */ |
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if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) |
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return; |
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/* Invalidate all ways for all processors */ |
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writel(0xFFFF, &scu->scu_inv_all); |
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/* Enable SCU - bit 0 */ |
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reg = readl(&scu->scu_ctrl); |
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reg |= SCU_CTRL_ENABLE; |
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writel(reg, &scu->scu_ctrl); |
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} |
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void init_pmc_scratch(void) |
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{ |
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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int i; |
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/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ |
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for (i = 0; i < 23; i++) |
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writel(0, &pmc->pmc_scratch1+i); |
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/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ |
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writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); |
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} |
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void cpu_start(void) |
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{ |
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; |
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/* enable JTAG */ |
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writel(0xC0, &pmt->pmt_cfg_ctl); |
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if (s_first_boot) { |
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/*
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* Need to set this before cold-booting, |
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* otherwise we'll end up in an infinite loop. |
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*/ |
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s_first_boot = 0; |
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cold_boot(); |
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} |
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} |
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void tegra2_start() |
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{ |
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if (s_first_boot) { |
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/* Init Debug UART Port (115200 8n1) */ |
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uart_init(); |
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/* Init PMC scratch memory */ |
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init_pmc_scratch(); |
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} |
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#ifdef CONFIG_ENABLE_CORTEXA9 |
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/* take the mpcore out of reset */ |
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cpu_start(); |
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/* configure cache */ |
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cache_configure(); |
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#endif |
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} |
@ -0,0 +1,104 @@ |
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/*
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* (C) Copyright 2010-2011 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <asm/types.h> |
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/* Stabilization delays, in usec */ |
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#define PLL_STABILIZATION_DELAY (300) |
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#define IO_STABILIZATION_DELAY (1000) |
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#define NVBL_PLLP_KHZ (216000) |
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#define PLLX_ENABLED (1 << 30) |
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#define CCLK_BURST_POLICY 0x20008888 |
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#define SUPER_CCLK_DIVIDER 0x80000000 |
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|
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/* Calculate clock fractional divider value from ref and target frequencies */ |
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#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) |
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/* Calculate clock frequency value from reference and clock divider value */ |
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#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) |
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|
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/* AVP/CPU ID */ |
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#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ |
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#define PG_UP_TAG_0 0x0 |
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#define CORESIGHT_UNLOCK 0xC5ACCE55; |
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|
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/* AP20-Specific Base Addresses */ |
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|
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/* AP20 Base physical address of SDRAM. */ |
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#define AP20_BASE_PA_SDRAM 0x00000000 |
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/* AP20 Base physical address of internal SRAM. */ |
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#define AP20_BASE_PA_SRAM 0x40000000 |
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/* AP20 Size of internal SRAM (256KB). */ |
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#define AP20_BASE_PA_SRAM_SIZE 0x00040000 |
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/* AP20 Base physical address of flash. */ |
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#define AP20_BASE_PA_NOR_FLASH 0xD0000000 |
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/* AP20 Base physical address of boot information table. */ |
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#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM |
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|
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/*
|
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* Super-temporary stacks for EXTREMELY early startup. The values chosen for |
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* these addresses must be valid on ALL SOCs because this value is used before |
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* we are able to differentiate between the SOC types. |
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* |
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* NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its |
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* stack is placed below the AVP stack. Once the CPU stack has been moved, |
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* the AVP is free to use the IRAM the CPU stack previously occupied if |
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* it should need to do so. |
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* |
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* NOTE: In multi-processor CPU complex configurations, each processor will have |
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* its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a |
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* limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a |
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* stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous |
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* CPU. |
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*/ |
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|
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/* Common AVP early boot stack limit */ |
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#define AVP_EARLY_BOOT_STACK_LIMIT \ |
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(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2)) |
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/* Common AVP early boot stack size */ |
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#define AVP_EARLY_BOOT_STACK_SIZE 0x1000 |
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/* Common CPU early boot stack limit */ |
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#define CPU_EARLY_BOOT_STACK_LIMIT \ |
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(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE) |
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/* Common CPU early boot stack size */ |
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#define CPU_EARLY_BOOT_STACK_SIZE 0x1000 |
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|
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#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) |
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#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) |
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#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) |
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|
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#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) |
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#define FLOW_MODE_STOP 2 |
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#define HALT_COP_EVENT_JTAG (1 << 28) |
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#define HALT_COP_EVENT_IRQ_1 (1 << 11) |
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#define HALT_COP_EVENT_FIQ_1 (1 << 9) |
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|
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/* Prototypes */ |
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|
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void tegra2_start(void); |
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void uart_init(void); |
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void udelay(unsigned long); |
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void cold_boot(void); |
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void cache_configure(void); |
@ -0,0 +1,58 @@ |
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/*
|
||||
* (C) Copyright 2011 |
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* Alexander Holler <holler@ahsoftware.de> |
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* |
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* Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37 |
||||
* |
||||
* See there for additional Copyrights. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
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*/ |
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#ifndef _EHCI_OMAP3_H_ |
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#define _EHCI_OMAP3_H_ |
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|
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/* USB/EHCI registers */ |
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#define OMAP3_USBTLL_BASE 0x48062000UL |
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#define OMAP3_UHH_BASE 0x48064000UL |
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#define OMAP3_EHCI_BASE 0x48064800UL |
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|
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/* TLL Register Set */ |
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#define OMAP_USBTLL_SYSCONFIG (0x10) |
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#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) |
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#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) |
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#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) |
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#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) |
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|
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#define OMAP_USBTLL_SYSSTATUS (0x14) |
||||
#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) |
||||
|
||||
/* UHH Register Set */ |
||||
#define OMAP_UHH_SYSCONFIG (0x10) |
||||
#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) |
||||
#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) |
||||
#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) |
||||
#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) |
||||
#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) |
||||
|
||||
#define OMAP_UHH_HOSTCONFIG (0x40) |
||||
#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) |
||||
#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) |
||||
#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) |
||||
|
||||
#endif /* _EHCI_OMAP3_H_ */ |
@ -0,0 +1,95 @@ |
||||
/*
|
||||
* (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _OMAP3_REGS_H |
||||
#define _OMAP3_REGS_H |
||||
|
||||
/*
|
||||
* Register definitions for OMAP3 processors. |
||||
*/ |
||||
|
||||
/*
|
||||
* GPMC_CONFIG1 - GPMC_CONFIG7 |
||||
*/ |
||||
|
||||
/* Values for GPMC_CONFIG1 - signal control parameters */ |
||||
#define WRAPBURST (1 << 31) |
||||
#define READMULTIPLE (1 << 30) |
||||
#define READTYPE (1 << 29) |
||||
#define WRITEMULTIPLE (1 << 28) |
||||
#define WRITETYPE (1 << 27) |
||||
#define CLKACTIVATIONTIME(x) (((x) & 3) << 25) |
||||
#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) |
||||
#define WAITREADMONITORING (1 << 22) |
||||
#define WAITWRITEMONITORING (1 << 21) |
||||
#define WAITMONITORINGTIME(x) (((x) & 3) << 18) |
||||
#define WAITPINSELECT(x) (((x) & 3) << 16) |
||||
#define DEVICESIZE(x) (((x) & 3) << 12) |
||||
#define DEVICESIZE_8BIT DEVICESIZE(0) |
||||
#define DEVICESIZE_16BIT DEVICESIZE(1) |
||||
#define DEVICETYPE(x) (((x) & 3) << 10) |
||||
#define DEVICETYPE_NOR DEVICETYPE(0) |
||||
#define DEVICETYPE_NAND DEVICETYPE(2) |
||||
#define MUXADDDATA (1 << 9) |
||||
#define TIMEPARAGRANULARITY (1 << 4) |
||||
#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) |
||||
|
||||
/* Values for GPMC_CONFIG2 - CS timing */ |
||||
#define CSWROFFTIME(x) (((x) & 0x1f) << 16) |
||||
#define CSRDOFFTIME(x) (((x) & 0x1f) << 8) |
||||
#define CSEXTRADELAY (1 << 7) |
||||
#define CSONTIME(x) (((x) & 0xf) << 0) |
||||
|
||||
/* Values for GPMC_CONFIG3 - nADV timing */ |
||||
#define ADVWROFFTIME(x) (((x) & 0x1f) << 16) |
||||
#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) |
||||
#define ADVEXTRADELAY (1 << 7) |
||||
#define ADVONTIME(x) (((x) & 0xf) << 0) |
||||
|
||||
/* Values for GPMC_CONFIG4 - nWE and nOE timing */ |
||||
#define WEOFFTIME(x) (((x) & 0x1f) << 24) |
||||
#define WEEXTRADELAY (1 << 23) |
||||
#define WEONTIME(x) (((x) & 0xf) << 16) |
||||
#define OEOFFTIME(x) (((x) & 0x1f) << 8) |
||||
#define OEEXTRADELAY (1 << 7) |
||||
#define OEONTIME(x) (((x) & 0xf) << 0) |
||||
|
||||
/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ |
||||
#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24) |
||||
#define RDACCESSTIME(x) (((x) & 0x1f) << 16) |
||||
#define WRCYCLETIME(x) (((x) & 0x1f) << 8) |
||||
#define RDCYCLETIME(x) (((x) & 0x1f) << 0) |
||||
|
||||
/* Values for GPMC_CONFIG6 - misc timings */ |
||||
#define WRACCESSTIME(x) (((x) & 0x1f) << 24) |
||||
#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) |
||||
#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) |
||||
#define CYCLE2CYCLESAMECSEN (1 << 7) |
||||
#define CYCLE2CYCLEDIFFCSEN (1 << 6) |
||||
#define BUSTURNAROUND(x) (((x) & 0xf) << 0) |
||||
|
||||
/* Values for GPMC_CONFIG7 - CS address mapping configuration */ |
||||
#define MASKADDRESS(x) (((x) & 0xf) << 8) |
||||
#define CSVALID (1 << 6) |
||||
#define BASEADDRESS(x) (((x) & 0x3f) << 0) |
||||
|
||||
#endif /* _OMAP3_REGS_H */ |
@ -0,0 +1,59 @@ |
||||
/*
|
||||
* Copyright (c) 2011, Google Inc. All rights reserved. |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _TEGRA2_GPIO_H_ |
||||
#define _TEGRA2_GPIO_H_ |
||||
|
||||
/*
|
||||
* The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports, |
||||
* each with 8 GPIOs. |
||||
*/ |
||||
#define TEGRA_GPIO_PORTS 4 /* The number of ports per bank */ |
||||
#define TEGRA_GPIO_BANKS 8 /* The number of banks */ |
||||
|
||||
/* GPIO Controller registers for a single bank */ |
||||
struct gpio_ctlr_bank { |
||||
uint gpio_config[TEGRA_GPIO_PORTS]; |
||||
uint gpio_dir_out[TEGRA_GPIO_PORTS]; |
||||
uint gpio_out[TEGRA_GPIO_PORTS]; |
||||
uint gpio_in[TEGRA_GPIO_PORTS]; |
||||
uint gpio_int_status[TEGRA_GPIO_PORTS]; |
||||
uint gpio_int_enable[TEGRA_GPIO_PORTS]; |
||||
uint gpio_int_level[TEGRA_GPIO_PORTS]; |
||||
uint gpio_int_clear[TEGRA_GPIO_PORTS]; |
||||
}; |
||||
|
||||
struct gpio_ctlr { |
||||
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; |
||||
}; |
||||
|
||||
#define GPIO_BANK(x) ((x) >> 5) |
||||
#define GPIO_PORT(x) (((x) >> 3) & 0x3) |
||||
#define GPIO_BIT(x) ((x) & 0x7) |
||||
|
||||
/*
|
||||
* GPIO_PI3 = Port I = 8, bit = 3. |
||||
* Seaboard: used for UART/SPI selection |
||||
* Harmony: not used |
||||
*/ |
||||
#define GPIO_PI3 ((8 << 3) | 3) |
||||
|
||||
#endif /* TEGRA2_GPIO_H_ */ |
@ -0,0 +1,43 @@ |
||||
/*
|
||||
* (C) Copyright 2010,2011 |
||||
* NVIDIA Corporation <www.nvidia.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _SCU_H_ |
||||
#define _SCU_H_ |
||||
|
||||
/* ARM Snoop Control Unit (SCU) registers */ |
||||
struct scu_ctlr { |
||||
uint scu_ctrl; /* SCU Control Register, offset 00 */ |
||||
uint scu_cfg; /* SCU Config Register, offset 04 */ |
||||
uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ |
||||
uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ |
||||
uint scu_reserved0[12]; /* reserved, offset 10-3C */ |
||||
uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ |
||||
uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ |
||||
uint scu_reserved1[2]; /* reserved, offset 48-4C */ |
||||
uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ |
||||
uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ |
||||
}; |
||||
|
||||
#define SCU_CTRL_ENABLE (1 << 0) |
||||
|
||||
#endif /* SCU_H */ |
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* arch/arm/include/asm/assembler.h |
||||
* |
||||
* Copyright (C) 1996-2000 Russell King |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* This file contains arm architecture specific defines |
||||
* for the different processors. |
||||
* |
||||
* Do not include any C declarations in this file - it is included by |
||||
* assembler source. |
||||
*/ |
||||
|
||||
/*
|
||||
* Endian independent macros for shifting bytes within registers. |
||||
*/ |
||||
#ifndef __ARMEB__ |
||||
#define pull lsr |
||||
#define push lsl |
||||
#define get_byte_0 lsl #0 |
||||
#define get_byte_1 lsr #8 |
||||
#define get_byte_2 lsr #16 |
||||
#define get_byte_3 lsr #24 |
||||
#define put_byte_0 lsl #0 |
||||
#define put_byte_1 lsl #8 |
||||
#define put_byte_2 lsl #16 |
||||
#define put_byte_3 lsl #24 |
||||
#else |
||||
#define pull lsl |
||||
#define push lsr |
||||
#define get_byte_0 lsr #24 |
||||
#define get_byte_1 lsr #16 |
||||
#define get_byte_2 lsr #8 |
||||
#define get_byte_3 lsl #0 |
||||
#define put_byte_0 lsl #24 |
||||
#define put_byte_1 lsl #16 |
||||
#define put_byte_2 lsl #8 |
||||
#define put_byte_3 lsl #0 |
||||
#endif |
||||
|
||||
/*
|
||||
* Data preload for architectures that support it |
||||
*/ |
||||
#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \ |
||||
defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
|
||||
defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \
|
||||
defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \
|
||||
defined(__ARM_ARCH_7R__) |
||||
#define PLD(code...) code |
||||
#else |
||||
#define PLD(code...) |
||||
#endif |
||||
|
||||
/*
|
||||
* Cache alligned |
||||
*/ |
||||
#define CALGN(code...) code |
@ -0,0 +1,241 @@ |
||||
/* |
||||
* linux/arch/arm/lib/memcpy.S |
||||
* |
||||
* Author: Nicolas Pitre |
||||
* Created: Sep 28, 2005 |
||||
* Copyright: MontaVista Software, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <asm/assembler.h> |
||||
|
||||
#define W(instr) instr |
||||
|
||||
#define LDR1W_SHIFT 0 |
||||
#define STR1W_SHIFT 0 |
||||
|
||||
.macro ldr1w ptr reg abort |
||||
W(ldr) \reg, [\ptr], #4 |
||||
.endm |
||||
|
||||
.macro ldr4w ptr reg1 reg2 reg3 reg4 abort |
||||
ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4} |
||||
.endm |
||||
|
||||
.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort |
||||
ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} |
||||
.endm |
||||
|
||||
.macro ldr1b ptr reg cond=al abort |
||||
ldr\cond\()b \reg, [\ptr], #1 |
||||
.endm |
||||
|
||||
.macro str1w ptr reg abort |
||||
W(str) \reg, [\ptr], #4 |
||||
.endm |
||||
|
||||
.macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort |
||||
stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} |
||||
.endm |
||||
|
||||
.macro str1b ptr reg cond=al abort |
||||
str\cond\()b \reg, [\ptr], #1 |
||||
.endm |
||||
|
||||
.macro enter reg1 reg2 |
||||
stmdb sp!, {r0, \reg1, \reg2} |
||||
.endm |
||||
|
||||
.macro exit reg1 reg2 |
||||
ldmfd sp!, {r0, \reg1, \reg2} |
||||
.endm |
||||
|
||||
.text |
||||
|
||||
/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ |
||||
|
||||
.globl memcpy
|
||||
memcpy: |
||||
|
||||
enter r4, lr |
||||
|
||||
subs r2, r2, #4 |
||||
blt 8f |
||||
ands ip, r0, #3 |
||||
PLD( pld [r1, #0] ) |
||||
bne 9f |
||||
ands ip, r1, #3 |
||||
bne 10f |
||||
|
||||
1: subs r2, r2, #(28) |
||||
stmfd sp!, {r5 - r8} |
||||
blt 5f |
||||
|
||||
CALGN( ands ip, r0, #31 ) |
||||
CALGN( rsb r3, ip, #32 ) |
||||
CALGN( sbcnes r4, r3, r2 ) @ C is always set here
|
||||
CALGN( bcs 2f ) |
||||
CALGN( adr r4, 6f ) |
||||
CALGN( subs r2, r2, r3 ) @ C gets set
|
||||
CALGN( add pc, r4, ip ) |
||||
|
||||
PLD( pld [r1, #0] ) |
||||
2: PLD( subs r2, r2, #96 ) |
||||
PLD( pld [r1, #28] ) |
||||
PLD( blt 4f ) |
||||
PLD( pld [r1, #60] ) |
||||
PLD( pld [r1, #92] ) |
||||
|
||||
3: PLD( pld [r1, #124] ) |
||||
4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f |
||||
subs r2, r2, #32 |
||||
str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f |
||||
bge 3b |
||||
PLD( cmn r2, #96 ) |
||||
PLD( bge 4b ) |
||||
|
||||
5: ands ip, r2, #28 |
||||
rsb ip, ip, #32 |
||||
#if LDR1W_SHIFT > 0 |
||||
lsl ip, ip, #LDR1W_SHIFT |
||||
#endif |
||||
addne pc, pc, ip @ C is always clear here
|
||||
b 7f |
||||
6: |
||||
.rept (1 << LDR1W_SHIFT) |
||||
W(nop) |
||||
.endr |
||||
ldr1w r1, r3, abort=20f |
||||
ldr1w r1, r4, abort=20f |
||||
ldr1w r1, r5, abort=20f |
||||
ldr1w r1, r6, abort=20f |
||||
ldr1w r1, r7, abort=20f |
||||
ldr1w r1, r8, abort=20f |
||||
ldr1w r1, lr, abort=20f |
||||
|
||||
#if LDR1W_SHIFT < STR1W_SHIFT |
||||
lsl ip, ip, #STR1W_SHIFT - LDR1W_SHIFT |
||||
#elif LDR1W_SHIFT > STR1W_SHIFT |
||||
lsr ip, ip, #LDR1W_SHIFT - STR1W_SHIFT |
||||
#endif |
||||
add pc, pc, ip |
||||
nop |
||||
.rept (1 << STR1W_SHIFT) |
||||
W(nop) |
||||
.endr |
||||
str1w r0, r3, abort=20f |
||||
str1w r0, r4, abort=20f |
||||
str1w r0, r5, abort=20f |
||||
str1w r0, r6, abort=20f |
||||
str1w r0, r7, abort=20f |
||||
str1w r0, r8, abort=20f |
||||
str1w r0, lr, abort=20f |
||||
|
||||
CALGN( bcs 2b ) |
||||
|
||||
7: ldmfd sp!, {r5 - r8} |
||||
|
||||
8: movs r2, r2, lsl #31 |
||||
ldr1b r1, r3, ne, abort=21f |
||||
ldr1b r1, r4, cs, abort=21f |
||||
ldr1b r1, ip, cs, abort=21f |
||||
str1b r0, r3, ne, abort=21f |
||||
str1b r0, r4, cs, abort=21f |
||||
str1b r0, ip, cs, abort=21f |
||||
|
||||
exit r4, pc |
||||
|
||||
9: rsb ip, ip, #4 |
||||
cmp ip, #2 |
||||
ldr1b r1, r3, gt, abort=21f |
||||
ldr1b r1, r4, ge, abort=21f |
||||
ldr1b r1, lr, abort=21f |
||||
str1b r0, r3, gt, abort=21f |
||||
str1b r0, r4, ge, abort=21f |
||||
subs r2, r2, ip |
||||
str1b r0, lr, abort=21f |
||||
blt 8b |
||||
ands ip, r1, #3 |
||||
beq 1b |
||||
|
||||
10: bic r1, r1, #3 |
||||
cmp ip, #2 |
||||
ldr1w r1, lr, abort=21f |
||||
beq 17f |
||||
bgt 18f |
||||
|
||||
|
||||
.macro forward_copy_shift pull push |
||||
|
||||
subs r2, r2, #28 |
||||
blt 14f |
||||
|
||||
CALGN( ands ip, r0, #31 ) |
||||
CALGN( rsb ip, ip, #32 ) |
||||
CALGN( sbcnes r4, ip, r2 ) @ C is always set here
|
||||
CALGN( subcc r2, r2, ip ) |
||||
CALGN( bcc 15f ) |
||||
|
||||
11: stmfd sp!, {r5 - r9} |
||||
|
||||
PLD( pld [r1, #0] ) |
||||
PLD( subs r2, r2, #96 ) |
||||
PLD( pld [r1, #28] ) |
||||
PLD( blt 13f ) |
||||
PLD( pld [r1, #60] ) |
||||
PLD( pld [r1, #92] ) |
||||
|
||||
12: PLD( pld [r1, #124] ) |
||||
13: ldr4w r1, r4, r5, r6, r7, abort=19f |
||||
mov r3, lr, pull #\pull |
||||
subs r2, r2, #32 |
||||
ldr4w r1, r8, r9, ip, lr, abort=19f |
||||
orr r3, r3, r4, push #\push |
||||
mov r4, r4, pull #\pull |
||||
orr r4, r4, r5, push #\push |
||||
mov r5, r5, pull #\pull |
||||
orr r5, r5, r6, push #\push |
||||
mov r6, r6, pull #\pull |
||||
orr r6, r6, r7, push #\push |
||||
mov r7, r7, pull #\pull |
||||
orr r7, r7, r8, push #\push |
||||
mov r8, r8, pull #\pull |
||||
orr r8, r8, r9, push #\push |
||||
mov r9, r9, pull #\pull |
||||
orr r9, r9, ip, push #\push |
||||
mov ip, ip, pull #\pull |
||||
orr ip, ip, lr, push #\push |
||||
str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f |
||||
bge 12b |
||||
PLD( cmn r2, #96 ) |
||||
PLD( bge 13b ) |
||||
|
||||
ldmfd sp!, {r5 - r9} |
||||
|
||||
14: ands ip, r2, #28 |
||||
beq 16f |
||||
|
||||
15: mov r3, lr, pull #\pull |
||||
ldr1w r1, lr, abort=21f |
||||
subs ip, ip, #4 |
||||
orr r3, r3, lr, push #\push |
||||
str1w r0, r3, abort=21f |
||||
bgt 15b |
||||
CALGN( cmp r2, #0 ) |
||||
CALGN( bge 11b ) |
||||
|
||||
16: sub r1, r1, #(\push / 8) |
||||
b 8b |
||||
|
||||
.endm |
||||
|
||||
|
||||
forward_copy_shift pull=8 push=24 |
||||
|
||||
17: forward_copy_shift pull=16 push=16 |
||||
|
||||
18: forward_copy_shift pull=24 push=8 |
||||
|
@ -0,0 +1,126 @@ |
||||
/* |
||||
* linux/arch/arm/lib/memset.S |
||||
* |
||||
* Copyright (C) 1995-2000 Russell King |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* ASM optimised string functions |
||||
*/ |
||||
#include <asm/assembler.h> |
||||
|
||||
.text |
||||
.align 5
|
||||
.word 0
|
||||
|
||||
1: subs r2, r2, #4 @ 1 do we have enough
|
||||
blt 5f @ 1 bytes to align with?
|
||||
cmp r3, #2 @ 1
|
||||
strltb r1, [r0], #1 @ 1
|
||||
strleb r1, [r0], #1 @ 1
|
||||
strb r1, [r0], #1 @ 1
|
||||
add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
|
||||
/* |
||||
* The pointer is now aligned and the length is adjusted. Try doing the |
||||
* memset again. |
||||
*/ |
||||
|
||||
.globl memset
|
||||
memset: |
||||
ands r3, r0, #3 @ 1 unaligned?
|
||||
bne 1b @ 1
|
||||
/* |
||||
* we know that the pointer in r0 is aligned to a word boundary. |
||||
*/ |
||||
orr r1, r1, r1, lsl #8 |
||||
orr r1, r1, r1, lsl #16 |
||||
mov r3, r1 |
||||
cmp r2, #16 |
||||
blt 4f |
||||
|
||||
#if ! CALGN(1)+0 |
||||
|
||||
/* |
||||
* We need an extra register for this loop - save the return address and |
||||
* use the LR |
||||
*/ |
||||
str lr, [sp, #-4]! |
||||
mov ip, r1 |
||||
mov lr, r1 |
||||
|
||||
2: subs r2, r2, #64 |
||||
stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time.
|
||||
stmgeia r0!, {r1, r3, ip, lr} |
||||
stmgeia r0!, {r1, r3, ip, lr} |
||||
stmgeia r0!, {r1, r3, ip, lr} |
||||
bgt 2b |
||||
ldmeqfd sp!, {pc} @ Now <64 bytes to go.
|
||||
/* |
||||
* No need to correct the count; we're only testing bits from now on
|
||||
*/ |
||||
tst r2, #32 |
||||
stmneia r0!, {r1, r3, ip, lr} |
||||
stmneia r0!, {r1, r3, ip, lr} |
||||
tst r2, #16 |
||||
stmneia r0!, {r1, r3, ip, lr} |
||||
ldr lr, [sp], #4 |
||||
|
||||
#else |
||||
|
||||
/* |
||||
* This version aligns the destination pointer in order to write |
||||
* whole cache lines at once. |
||||
*/ |
||||
|
||||
stmfd sp!, {r4-r7, lr} |
||||
mov r4, r1 |
||||
mov r5, r1 |
||||
mov r6, r1 |
||||
mov r7, r1 |
||||
mov ip, r1 |
||||
mov lr, r1 |
||||
|
||||
cmp r2, #96 |
||||
tstgt r0, #31 |
||||
ble 3f |
||||
|
||||
and ip, r0, #31 |
||||
rsb ip, ip, #32 |
||||
sub r2, r2, ip |
||||
movs ip, ip, lsl #(32 - 4) |
||||
stmcsia r0!, {r4, r5, r6, r7} |
||||
stmmiia r0!, {r4, r5} |
||||
tst ip, #(1 << 30) |
||||
mov ip, r1 |
||||
strne r1, [r0], #4 |
||||
|
||||
3: subs r2, r2, #64 |
||||
stmgeia r0!, {r1, r3-r7, ip, lr} |
||||
stmgeia r0!, {r1, r3-r7, ip, lr} |
||||
bgt 3b |
||||
ldmeqfd sp!, {r4-r7, pc} |
||||
|
||||
tst r2, #32 |
||||
stmneia r0!, {r1, r3-r7, ip, lr} |
||||
tst r2, #16 |
||||
stmneia r0!, {r4-r7} |
||||
ldmfd sp!, {r4-r7, lr} |
||||
|
||||
#endif |
||||
|
||||
4: tst r2, #8 |
||||
stmneia r0!, {r1, r3} |
||||
tst r2, #4 |
||||
strne r1, [r0], #4 |
||||
/* |
||||
* When we get here, we've got less than 4 bytes to zero. We |
||||
* may have an unaligned pointer as well. |
||||
*/ |
||||
5: tst r2, #2 |
||||
strneb r1, [r0], #1 |
||||
strneb r1, [r0], #1 |
||||
tst r2, #1 |
||||
strneb r1, [r0], #1 |
||||
mov pc, lr |
@ -1,22 +0,0 @@ |
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
# Linux-Kernel is expected to be at 0x60008000
|
||||
#
|
||||
CONFIG_SYS_TEXT_BASE = 0x60800000
|
@ -0,0 +1,45 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* CompuLab, Ltd. <www.compulab.co.il> |
||||
* |
||||
* Author: Igor Grinberg <grinberg@compulab.co.il> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc. |
||||
*/ |
||||
#include <common.h> |
||||
#include <status_led.h> |
||||
#include <asm/arch/gpio.h> |
||||
|
||||
static unsigned int leds[] = { GREEN_LED_GPIO }; |
||||
|
||||
void __led_init(led_id_t mask, int state) |
||||
{ |
||||
if (omap_request_gpio(leds[mask]) != 0) { |
||||
printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]); |
||||
return; |
||||
} |
||||
|
||||
omap_set_gpio_direction(leds[mask], 0); |
||||
} |
||||
|
||||
void __led_set(led_id_t mask, int state) |
||||
{ |
||||
omap_set_gpio_dataout(leds[mask], state == STATUS_LED_ON); |
||||
} |
||||
|
||||
void __led_toggle(led_id_t mask) |
||||
{ |
||||
omap_set_gpio_dataout(leds[mask], !omap_get_gpio_datain(leds[mask])); |
||||
} |
@ -0,0 +1,187 @@ |
||||
/*
|
||||
* (C) Copyright 2011 Comelit Group SpA |
||||
* Luca Ceresoli <luca.ceresoli@comelit.it> |
||||
* |
||||
* Based on board/ti/beagle/beagle.c: |
||||
* (C) Copyright 2004-2008 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* Author : |
||||
* Sunil Kumar <sunilsaini05@gmail.com> |
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com> |
||||
* |
||||
* Derived from Beagle Board and 3430 SDP code by |
||||
* Richard Woodruff <r-woodruff2@ti.com> |
||||
* Syed Mohammed Khasim <khasim@ti.com> |
||||
* |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#include <common.h> |
||||
#include <netdev.h> |
||||
#include <twl4030.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/omap3-regs.h> |
||||
#include <asm/arch/mux.h> |
||||
#include <asm/arch/mem.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/mach-types.h> |
||||
#include "dig297.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_CMD_NET |
||||
static void setup_net_chip(void); |
||||
|
||||
#define NET_LAN9221_RESET_GPIO 12 |
||||
|
||||
/* GPMC CS 5 connected to an SMSC LAN9220 ethernet controller */ |
||||
#define NET_LAN9220_GPMC_CONFIG1 (DEVICESIZE_16BIT) |
||||
#define NET_LAN9220_GPMC_CONFIG2 (CSWROFFTIME(8) | \ |
||||
CSRDOFFTIME(7) | \
|
||||
ADVONTIME(1)) |
||||
#define NET_LAN9220_GPMC_CONFIG3 (ADVWROFFTIME(2) | \ |
||||
ADVRDOFFTIME(2) | \
|
||||
ADVONTIME(1)) |
||||
#define NET_LAN9220_GPMC_CONFIG4 (WEOFFTIME(8) | \ |
||||
WEONTIME(1) | \
|
||||
OEOFFTIME(7)| \
|
||||
OEONTIME(1)) |
||||
#define NET_LAN9220_GPMC_CONFIG5 (PAGEBURSTACCESSTIME(0) | \ |
||||
RDACCESSTIME(6) | \
|
||||
WRCYCLETIME(0x1D) | \
|
||||
RDCYCLETIME(0x1D)) |
||||
#define NET_LAN9220_GPMC_CONFIG6 ((1 << 31) | \ |
||||
WRACCESSTIME(0x1D) | \
|
||||
WRDATAONADMUXBUS(3)) |
||||
|
||||
static const u32 gpmc_lan_config[] = { |
||||
NET_LAN9220_GPMC_CONFIG1, |
||||
NET_LAN9220_GPMC_CONFIG2, |
||||
NET_LAN9220_GPMC_CONFIG3, |
||||
NET_LAN9220_GPMC_CONFIG4, |
||||
NET_LAN9220_GPMC_CONFIG5, |
||||
NET_LAN9220_GPMC_CONFIG6, |
||||
/* CONFIG7: computed by enable_gpmc_cs_config() */ |
||||
}; |
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
/*
|
||||
* Routine: board_init |
||||
* Description: Early hardware init. |
||||
*/ |
||||
int board_init(void) |
||||
{ |
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
||||
/* board id for Linux */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CPS; |
||||
/* boot param addr */ |
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Routine: misc_init_r |
||||
* Description: Configure board specific parts |
||||
*/ |
||||
int misc_init_r(void) |
||||
{ |
||||
struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE; |
||||
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; |
||||
|
||||
twl4030_power_init(); |
||||
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); |
||||
|
||||
/*
|
||||
* GPIO list |
||||
* - 159 OUT (GPIO5+31): reset for remote camera interface connector. |
||||
* - 19 OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn). |
||||
* - 20 OUT (GPIO1+20): handset amplifier (1=on, 0=shdn). |
||||
*/ |
||||
|
||||
/* Configure GPIOs to output */ |
||||
writel(~(GPIO19 | GPIO20), &gpio1_base->oe); |
||||
writel(~(GPIO31), &gpio5_base->oe); |
||||
|
||||
/* Set GPIO values */ |
||||
writel((GPIO19 | GPIO20), &gpio1_base->setdataout); |
||||
writel(0, &gpio5_base->setdataout); |
||||
|
||||
#if defined(CONFIG_CMD_NET) |
||||
setup_net_chip(); |
||||
#endif |
||||
|
||||
dieid_num_r(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Routine: set_muxconf_regs |
||||
* Description: Setting up the configuration Mux registers specific to the |
||||
* hardware. Many pins need to be moved from protect to primary |
||||
* mode. |
||||
*/ |
||||
void set_muxconf_regs(void) |
||||
{ |
||||
MUX_DIG297(); |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_NET |
||||
/*
|
||||
* Routine: setup_net_chip |
||||
* Description: Setting up the configuration GPMC registers specific to the |
||||
* Ethernet hardware. |
||||
*/ |
||||
static void setup_net_chip(void) |
||||
{ |
||||
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
||||
|
||||
/* Configure GPMC registers */ |
||||
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], |
||||
CONFIG_SMC911X_BASE, GPMC_SIZE_16M); |
||||
|
||||
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ |
||||
writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); |
||||
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ |
||||
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); |
||||
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ |
||||
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, |
||||
&ctrl_base->gpmc_nadv_ale); |
||||
|
||||
/* Make GPIO 12 as output pin and send a magic pulse through it */ |
||||
if (!omap_request_gpio(NET_LAN9221_RESET_GPIO)) { |
||||
omap_set_gpio_direction(NET_LAN9221_RESET_GPIO, 0); |
||||
omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1); |
||||
udelay(1); |
||||
omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 0); |
||||
udelay(31000); /* Should be >= 30ms according to datasheet */ |
||||
omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1); |
||||
} |
||||
} |
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int rc = 0; |
||||
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
||||
return rc; |
||||
} |
@ -0,0 +1,383 @@ |
||||
/*
|
||||
* (C) Copyright 2011 Comelit Group SpA |
||||
* Luca Ceresoli <luca.ceresoli@comelit.it> |
||||
* |
||||
* Based on board/ti/beagle/beagle.h: |
||||
* (C) Copyright 2008 |
||||
* Dirk Behme <dirk.behme@gmail.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef _DIG297_H_ |
||||
#define _DIG297_H_ |
||||
|
||||
const omap3_sysinfo sysinfo = { |
||||
DDR_STACKED, |
||||
"OMAP3 DIG297 board", |
||||
"NAND", |
||||
}; |
||||
|
||||
/*
|
||||
* IEN - Input Enable |
||||
* IDIS - Input Disable |
||||
* PTD - Pull type Down |
||||
* PTU - Pull type Up |
||||
* DIS - Pull type selection is inactive |
||||
* EN - Pull type selection is active |
||||
* M0 - Mode 0 |
||||
* The commented string gives the final mux configuration for that pin |
||||
*/ |
||||
#define MUX_DIG297() \ |
||||
/*SDRC*/\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\
|
||||
/*GPMC*/\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*NAND*/\
|
||||
/* GPMC_nCS1/2: not available on CUS package*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\
|
||||
/* GPMC_WAIT2: not available on CUS package*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\
|
||||
/* GPMC_CLK: NC (only asyncronous peripherals are connected) */\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
|
||||
/* GPMC_WAIT1: not available on CUS package*/\
|
||||
/*DSS*/\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
|
||||
/* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTU | EN | M7))\
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
|
||||
/*CAMERA*/\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
|
||||
/*Audio Interface */\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
|
||||
/*Expansion card */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
|
||||
/*Wireless LAN */\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
|
||||
/*Bluetooth*/\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
|
||||
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
|
||||
/*Modem Interface */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
|
||||
MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
|
||||
/*Serial Interface*/\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
|
||||
/* USB EHCI (port 2) */\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
|
||||
/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\
|
||||
/*
|
||||
* McSPI1_CLK. |
||||
* IEN needed fot the McSPI to "receive" the clock and be able to |
||||
* sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/
|
||||
* omap_applications_processors/f/42/p/29444/102394.aspx#102394 |
||||
*/\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTD | EN | M0)) /*McSPI1_SIMO*/\
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) /*McSPI1_SOMI*/\
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0*/\
|
||||
/* MCSPI2: to HIMAX TFT controller.*/\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IDIS | PTD | EN | M0)) /*MCSPI2_CLK*/\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | EN | M0)) /*MCSPI3_SIMO*/\
|
||||
/* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IDIS | PTU | DIS | M7))\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | EN | M0)) /*MCSPI3_CS0*/\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\
|
||||
/* GPIO */\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M4)) /*GPIO_12*/\
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) /*GPIO_13*/\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M4)) /*GPIO_14*/\
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | EN | M4)) /*GPIO_15*/\
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | EN | M4)) /*GPIO_16*/\
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M4)) /*GPIO_17*/\
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | EN | M4)) /*GPIO_18*/\
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | EN | M4)) /*GPIO_19*/\
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | EN | M4)) /*GPIO_20*/\
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | EN | M4)) /*GPIO_21*/\
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M4)) /*GPIO_23*/\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) /*GPIO_24*/\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | EN | M4)) /*GPIO_25*/\
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | EN | M4)) /*GPIO_26*/\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | EN | M4)) /*GPIO_27*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M4)) /*GPIO_156*/\
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
|
||||
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
|
||||
MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | EN | M4)) /*GPIO_164*/\
|
||||
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | DIS | M4)) /*GPIO_170*/\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) /*GPIO_177*/\
|
||||
/*Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */ |
||||
|
||||
#endif |
@ -1 +0,0 @@ |
||||
CONFIG_SYS_TEXT_BASE = 0x21f00000
|
@ -1 +0,0 @@ |
||||
CONFIG_SYS_TEXT_BASE = 0x21F00000
|
@ -1,25 +0,0 @@ |
||||
#
|
||||
# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
CONFIG_SYS_TEXT_BASE = 0x97800000
|
||||
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
|
||||
ALL += $(obj)u-boot.imx
|
@ -0,0 +1,33 @@ |
||||
/*
|
||||
* (C) Copyright 2010,2011 |
||||
* NVIDIA Corporation <www.nvidia.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _BOARD_H_ |
||||
#define _BOARD_H_ |
||||
|
||||
void tegra2_start(void); |
||||
void clock_init(void); |
||||
void pinmux_init(void); |
||||
void gpio_init(void); |
||||
void gpio_config_uart(void); |
||||
|
||||
#endif /* BOARD_H */ |
@ -0,0 +1,34 @@ |
||||
/*
|
||||
* (C) Copyright 2010,2011 |
||||
* NVIDIA Corporation <www.nvidia.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/tegra2.h> |
||||
|
||||
/*
|
||||
* Routine: gpio_config_uart |
||||
* Description: Does nothing on Harmony - no conflict w/SPI. |
||||
*/ |
||||
void gpio_config_uart(void) |
||||
{ |
||||
} |
@ -0,0 +1,52 @@ |
||||
/*
|
||||
* (C) Copyright 2010,2011 |
||||
* NVIDIA Corporation <www.nvidia.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/tegra2.h> |
||||
#include <asm/arch/gpio.h> |
||||
|
||||
/*
|
||||
* Routine: gpio_config_uart |
||||
* Description: Force GPIO_PI3 low on Seaboard so UART4 works. |
||||
*/ |
||||
void gpio_config_uart(void) |
||||
{ |
||||
int gp = GPIO_PI3; |
||||
struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; |
||||
struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; |
||||
u32 val; |
||||
|
||||
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ |
||||
val = readl(&bank->gpio_config[GPIO_PORT(gp)]); |
||||
val |= 1 << GPIO_BIT(gp); |
||||
writel(val, &bank->gpio_config[GPIO_PORT(gp)]); |
||||
|
||||
val = readl(&bank->gpio_out[GPIO_PORT(gp)]); |
||||
val &= ~(1 << GPIO_BIT(gp)); |
||||
writel(val, &bank->gpio_out[GPIO_PORT(gp)]); |
||||
|
||||
val = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]); |
||||
val |= 1 << GPIO_BIT(gp); |
||||
writel(val, &bank->gpio_dir_out[GPIO_PORT(gp)]); |
||||
} |
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Reference in new issue