LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>master
Mingkai Hu
9 years ago
committed by
York Sun
parent
8281c58fd4
commit
f3a8e2b7d4
@ -0,0 +1,86 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/fsl_serdes.h> |
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#include <asm/arch/immap_lsch2.h> |
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struct serdes_config { |
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u32 protocol; |
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u8 lanes[SRDS_MAX_LANES]; |
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}; |
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static struct serdes_config serdes1_cfg_tbl[] = { |
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/* SerDes 1 */ |
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{0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} }, |
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{0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} }, |
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{0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} }, |
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{0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} }, |
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{0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} }, |
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{0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} }, |
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{0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, |
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PCIE3} }, |
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{0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} }, |
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{0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} }, |
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{0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} }, |
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{0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} }, |
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{0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} }, |
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{0x9998, {PCIE1, PCIE2, PCIE3, SATA1} }, |
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{0x6058, {PCIE1, PCIE1, PCIE2, SATA1} }, |
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{0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} }, |
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{0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} }, |
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{0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} }, |
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{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, |
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SGMII_FM1_DTSEC6} }, |
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{} |
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}; |
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static struct serdes_config *serdes_cfg_tbl[] = { |
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serdes1_cfg_tbl, |
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}; |
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) |
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{ |
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struct serdes_config *ptr; |
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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ptr = serdes_cfg_tbl[serdes]; |
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while (ptr->protocol) { |
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if (ptr->protocol == cfg) |
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return ptr->lanes[lane]; |
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ptr++; |
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} |
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return 0; |
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} |
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int is_serdes_prtcl_valid(int serdes, u32 prtcl) |
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{ |
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int i; |
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struct serdes_config *ptr; |
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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ptr = serdes_cfg_tbl[serdes]; |
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while (ptr->protocol) { |
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if (ptr->protocol == prtcl) |
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break; |
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ptr++; |
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} |
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if (!ptr->protocol) |
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return 0; |
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for (i = 0; i < SRDS_MAX_LANES; i++) { |
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if (ptr->lanes[i] != NONE) |
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return 1; |
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} |
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return 0; |
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} |
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@ -0,0 +1,16 @@ |
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if TARGET_LS1043ARDB |
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config SYS_BOARD |
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default "ls1043ardb" |
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config SYS_VENDOR |
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default "freescale" |
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config SYS_SOC |
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default "fsl-layerscape" |
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config SYS_CONFIG_NAME |
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default "ls1043ardb" |
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endif |
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@ -0,0 +1,7 @@ |
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LS1043A BOARD |
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M: Mingkai Hu <Mingkai.hu@freescale.com> |
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S: Maintained |
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F: board/freescale/ls1043ardb/ |
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F: board/freescale/ls1043ardb/ls1043ardb.c |
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F: include/configs/ls1043ardb.h |
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F: configs/ls1043ardb_defconfig |
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@ -0,0 +1,9 @@ |
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#
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# Copyright 2015 Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpld.o
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obj-y += ddr.o
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obj-y += ls1043ardb.o
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@ -0,0 +1,85 @@ |
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Overview |
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-------- |
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The LS1043A Reference Design Board (RDB) is a high-performance computing, |
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evaluation, and development platform that supports the QorIQ LS1043A |
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LayerScape Architecture processor. The LS1043ARDB provides SW development |
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platform for the Freescale LS1043A processor series, with a complete |
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debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. |
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LS1043A SoC Overview |
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-------------------- |
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The LS1043A integrated multicore processor combines four ARM Cortex-A53 |
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processor cores with datapath acceleration optimized for L2/3 packet |
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processing, single pass security offload and robust traffic management |
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and quality of service. |
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The LS1043A SoC includes the following function and features: |
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- Four 64-bit ARM Cortex-A53 CPUs |
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- 1 MB unified L2 Cache |
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- One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving |
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support |
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration the |
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the following functions: |
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- Packet parsing, classification, and distribution (FMan) |
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- Queue management for scheduling, packet sequencing, and congestion |
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management (QMan) |
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- Hardware buffer management for buffer allocation and de-allocation (BMan) |
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- Cryptography acceleration (SEC) |
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- Ethernet interfaces by FMan |
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- Up to 1 x XFI supporting 10G interface |
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- Up to 1 x QSGMII |
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- Up to 4 x SGMII supporting 1000Mbps |
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- Up to 2 x SGMII supporting 2500Mbps |
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- Up to 2 x RGMII supporting 1000Mbps |
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- High-speed peripheral interfaces |
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- Three PCIe 2.0 controllers, one supporting x4 operation |
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- One serial ATA (SATA 3.0) controllers |
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- Additional peripheral interfaces |
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- Three high-speed USB 3.0 controllers with integrated PHY |
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- Enhanced secure digital host controller (eSDXC/eMMC) |
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- Quad Serial Peripheral Interface (QSPI) Controller |
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- Serial peripheral interface (SPI) controller |
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- Four I2C controllers |
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- Two DUARTs |
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- Integrated flash controller supporting NAND and NOR flash |
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- QorIQ platform's trust architecture 2.1 |
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LS1043ARDB board Overview |
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----------------------- |
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- SERDES Connections, 4 lanes supporting: |
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- PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and |
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standard PCIe card |
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- QSGMII with x4 RJ45 connector |
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- XFI with x1 RJ45 connector |
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- DDR Controller |
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- 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s |
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-IFC/Local Bus |
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- One 128MB NOR flash 16-bit data bus |
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- One 512 MB NAND flash with ECC support |
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- CPLD connection |
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- USB 3.0 |
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- Two super speed USB 3.0 Type A ports |
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- SDHC: connects directly to a full SD/MMC slot |
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- DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) |
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- 4 I2C controllers |
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- UART |
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- Two 4-pin serial ports at up to 115.2 Kbit/s |
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- Two DB9 D-Type connectors supporting one Serial port each |
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- ARM JTAG support |
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Memory map from core's view |
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---------------------------- |
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Start Address End Address Description Size |
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0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB |
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0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB |
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0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB |
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0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB |
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0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB |
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0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB |
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0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB |
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0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB |
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0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB |
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Booting Options |
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--------------- |
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a) NOR boot |
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@ -0,0 +1,115 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Freescale LS1043ARDB board-specific CPLD controlling supports. |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/io.h> |
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#include "cpld.h" |
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u8 cpld_read(unsigned int reg) |
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{ |
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void *p = (void *)CONFIG_SYS_CPLD_BASE; |
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return in_8(p + reg); |
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} |
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void cpld_write(unsigned int reg, u8 value) |
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{ |
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void *p = (void *)CONFIG_SYS_CPLD_BASE; |
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out_8(p + reg, value); |
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} |
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/* Set the boot bank to the alternate bank */ |
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void cpld_set_altbank(void) |
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{ |
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u8 reg4 = CPLD_READ(soft_mux_on); |
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u8 reg7 = CPLD_READ(vbank); |
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CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL); |
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reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; |
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CPLD_WRITE(vbank, reg7); |
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CPLD_WRITE(system_rst, 1); |
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} |
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/* Set the boot bank to the default bank */ |
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void cpld_set_defbank(void) |
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{ |
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CPLD_WRITE(global_rst, 1); |
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} |
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#ifdef DEBUG |
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static void cpld_dump_regs(void) |
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{ |
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printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); |
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printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); |
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printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); |
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printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); |
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printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); |
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printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); |
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printf("vbank = %x\n", CPLD_READ(vbank)); |
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printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); |
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printf("uart_sel = %x\n", CPLD_READ(uart_sel)); |
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printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); |
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printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel)); |
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printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel)); |
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printf("status_led = %x\n", CPLD_READ(status_led)); |
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putc('\n'); |
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} |
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#endif |
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void cpld_rev_bit(unsigned char *value) |
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{ |
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u8 rev_val, val; |
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int i; |
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val = *value; |
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rev_val = val & 1; |
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for (i = 1; i <= 7; i++) { |
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val >>= 1; |
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rev_val <<= 1; |
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rev_val |= val & 1; |
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} |
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*value = rev_val; |
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} |
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int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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int rc = 0; |
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if (argc <= 1) |
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return cmd_usage(cmdtp); |
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if (strcmp(argv[1], "reset") == 0) { |
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if (strcmp(argv[2], "altbank") == 0) |
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cpld_set_altbank(); |
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else |
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cpld_set_defbank(); |
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#ifdef DEBUG |
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} else if (strcmp(argv[1], "dump") == 0) { |
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cpld_dump_regs(); |
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#endif |
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} else { |
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rc = cmd_usage(cmdtp); |
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} |
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return rc; |
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} |
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U_BOOT_CMD( |
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cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, |
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"Reset the board or alternate bank", |
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"reset: reset to default bank\n" |
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"cpld reset altbank: reset to alternate bank\n" |
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#ifdef DEBUG |
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"cpld dump - display the CPLD registers\n" |
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#endif |
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); |
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@ -0,0 +1,43 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CPLD_H__ |
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#define __CPLD_H__ |
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/*
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* CPLD register set of LS1043ARDB board-specific. |
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*/ |
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struct cpld_data { |
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u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ |
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u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ |
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u8 pcba_ver; /* 0x2 - PCBA Revision Register */ |
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u8 system_rst; /* 0x3 - system reset register */ |
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u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ |
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u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */ |
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u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */ |
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u8 vbank; /* 0x7 - Flash bank selection Control */ |
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u8 sysclk_sel; /* 0x8 - */ |
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u8 uart_sel; /* 0x9 - */ |
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u8 sd1refclk_sel; /* 0xA - */ |
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u8 tdmclk_mux_sel; /* 0xB - */ |
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u8 sdhc_spics_sel; /* 0xC - */ |
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u8 status_led; /* 0xD - */ |
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u8 global_rst; /* 0xE - */ |
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}; |
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u8 cpld_read(unsigned int reg); |
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void cpld_write(unsigned int reg, u8 value); |
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void cpld_rev_bit(unsigned char *value); |
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) |
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#define CPLD_WRITE(reg, value) \ |
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cpld_write(offsetof(struct cpld_data, reg), value) |
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/* CPLD on IFC */ |
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#define CPLD_SW_MUX_BANK_SEL 0x40 |
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#define CPLD_BANK_SEL_MASK 0x07 |
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#define CPLD_BANK_SEL_ALTBANK 0x04 |
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#endif |
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@ -0,0 +1,191 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <fsl_ddr_sdram.h> |
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#include <fsl_ddr_dimm_params.h> |
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#include "ddr.h" |
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#ifdef CONFIG_FSL_DEEP_SLEEP |
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#include <fsl_sleep.h> |
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#endif |
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DECLARE_GLOBAL_DATA_PTR; |
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void fsl_ddr_board_options(memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num) |
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{ |
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
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ulong ddr_freq; |
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if (ctrl_num > 1) { |
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printf("Not supported controller number %d\n", ctrl_num); |
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return; |
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} |
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if (!pdimm->n_ranks) |
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return; |
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pbsp = udimms[0]; |
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/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table. |
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*/ |
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ddr_freq = get_ddr_freq(0) / 1000000; |
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while (pbsp->datarate_mhz_high) { |
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if (pbsp->n_ranks == pdimm->n_ranks) { |
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if (ddr_freq <= pbsp->datarate_mhz_high) { |
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popts->clk_adjust = pbsp->clk_adjust; |
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popts->wrlvl_start = pbsp->wrlvl_start; |
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
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popts->cpo_override = pbsp->cpo_override; |
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popts->write_data_delay = |
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pbsp->write_data_delay; |
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goto found; |
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} |
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pbsp_highest = pbsp; |
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} |
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pbsp++; |
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} |
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if (pbsp_highest) { |
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printf("Error: board specific timing not found for %lu MT/s\n", |
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ddr_freq); |
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printf("Trying to use the highest speed (%u) parameters\n", |
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pbsp_highest->datarate_mhz_high); |
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popts->clk_adjust = pbsp_highest->clk_adjust; |
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popts->wrlvl_start = pbsp_highest->wrlvl_start; |
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
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} else { |
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panic("DIMM is not supported by this board"); |
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} |
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found: |
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", |
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); |
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/* force DDR bus width to 32 bits */ |
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popts->data_bus_width = 1; |
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popts->otf_burst_chop_en = 0; |
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popts->burst_length = DDR_BL8; |
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/*
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* Factors to consider for half-strength driver enable: |
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* - number of DIMMs installed |
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*/ |
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popts->half_strength_driver_enable = 1; |
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/*
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* Write leveling override |
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*/ |
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popts->wrlvl_override = 1; |
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popts->wrlvl_sample = 0xf; |
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/*
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* Rtt and Rtt_WR override |
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*/ |
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popts->rtt_override = 0; |
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/* Enable ZQ calibration */ |
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popts->zq_en = 1; |
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); |
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | |
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DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ |
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} |
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/* DDR model number: MT40A512M8HX-093E */ |
||||
#ifdef CONFIG_SYS_DDR_RAW_TIMING |
||||
dimm_params_t ddr_raw_timing = { |
||||
.n_ranks = 1, |
||||
.rank_density = 2147483648u, |
||||
.capacity = 2147483648u, |
||||
.primary_sdram_width = 32, |
||||
.ec_sdram_width = 0, |
||||
.registered_dimm = 0, |
||||
.mirrored_dimm = 0, |
||||
.n_row_addr = 15, |
||||
.n_col_addr = 10, |
||||
.bank_addr_bits = 0, |
||||
.bank_group_bits = 2, |
||||
.edc_config = 0, |
||||
.burst_lengths_bitmask = 0x0c, |
||||
|
||||
.tckmin_x_ps = 938, |
||||
.tckmax_ps = 1500, |
||||
.caslat_x = 0x000DFA00, |
||||
.taa_ps = 13500, |
||||
.trcd_ps = 13500, |
||||
.trp_ps = 13500, |
||||
.tras_ps = 33000, |
||||
.trc_ps = 46500, |
||||
.trfc1_ps = 260000, |
||||
.trfc2_ps = 160000, |
||||
.trfc4_ps = 110000, |
||||
.tfaw_ps = 21000, |
||||
.trrds_ps = 3700, |
||||
.trrdl_ps = 5300, |
||||
.tccdl_ps = 5355, |
||||
.refresh_rate_ps = 7800000, |
||||
.dq_mapping[0] = 0x0, |
||||
.dq_mapping[1] = 0x0, |
||||
.dq_mapping[2] = 0x0, |
||||
.dq_mapping[3] = 0x0, |
||||
.dq_mapping[4] = 0x0, |
||||
.dq_mapping[5] = 0x0, |
||||
.dq_mapping[6] = 0x0, |
||||
.dq_mapping[7] = 0x0, |
||||
.dq_mapping[8] = 0x0, |
||||
.dq_mapping[9] = 0x0, |
||||
.dq_mapping[10] = 0x0, |
||||
.dq_mapping[11] = 0x0, |
||||
.dq_mapping[12] = 0x0, |
||||
.dq_mapping[13] = 0x0, |
||||
.dq_mapping[14] = 0x0, |
||||
.dq_mapping[15] = 0x0, |
||||
.dq_mapping[16] = 0x0, |
||||
.dq_mapping[17] = 0x0, |
||||
.dq_mapping_ors = 0, |
||||
}; |
||||
|
||||
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, |
||||
unsigned int controller_number, |
||||
unsigned int dimm_number) |
||||
{ |
||||
static const char dimm_model[] = "Fixed DDR on board"; |
||||
|
||||
if (((controller_number == 0) && (dimm_number == 0)) || |
||||
((controller_number == 1) && (dimm_number == 0))) { |
||||
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); |
||||
memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); |
||||
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
phys_size_t dram_size; |
||||
|
||||
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) |
||||
puts("Initializing DDR....\n"); |
||||
dram_size = fsl_ddr_sdram(); |
||||
#else |
||||
dram_size = fsl_ddr_sdram_size(); |
||||
#endif |
||||
#ifdef CONFIG_FSL_DEEP_SLEEP |
||||
fsl_dp_ddr_restore(); |
||||
#endif |
||||
|
||||
return dram_size; |
||||
} |
||||
|
||||
void dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
||||
gd->bd->bi_dram[0].size = gd->ram_size; |
||||
} |
||||
@ -0,0 +1,45 @@ |
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __DDR_H__ |
||||
#define __DDR_H__ |
||||
struct board_specific_parameters { |
||||
u32 n_ranks; |
||||
u32 datarate_mhz_high; |
||||
u32 rank_gb; |
||||
u32 clk_adjust; |
||||
u32 wrlvl_start; |
||||
u32 wrlvl_ctl_2; |
||||
u32 wrlvl_ctl_3; |
||||
u32 cpo_override; |
||||
u32 write_data_delay; |
||||
u32 force_2t; |
||||
}; |
||||
|
||||
/*
|
||||
* These tables contain all valid speeds we want to override with board |
||||
* specific parameters. datarate_mhz_high values need to be in ascending order |
||||
* for each n_ranks group. |
||||
*/ |
||||
static const struct board_specific_parameters udimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
||||
*/ |
||||
#ifdef CONFIG_SYS_FSL_DDR4 |
||||
{1, 1666, 0, 6, 7, 0x07090800, 0x00000000,}, |
||||
{1, 1900, 0, 6, 7, 0x07090800, 0x00000000,}, |
||||
{1, 2200, 0, 6, 7, 0x07090800, 0x00000000,}, |
||||
#endif |
||||
{} |
||||
}; |
||||
|
||||
static const struct board_specific_parameters *udimms[] = { |
||||
udimm0, |
||||
}; |
||||
|
||||
#endif |
||||
@ -0,0 +1,131 @@ |
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/fsl_serdes.h> |
||||
#include <asm/arch/soc.h> |
||||
#include <hwconfig.h> |
||||
#include <ahci.h> |
||||
#include <scsi.h> |
||||
#include <fsl_csu.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <fsl_ifc.h> |
||||
#include "cpld.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; |
||||
u8 cfg_rcw_src1, cfg_rcw_src2; |
||||
u32 cfg_rcw_src; |
||||
u32 sd1refclk_sel; |
||||
|
||||
printf("Board: LS1043ARDB, boot from "); |
||||
|
||||
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); |
||||
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); |
||||
cpld_rev_bit(&cfg_rcw_src1); |
||||
cfg_rcw_src = cfg_rcw_src1; |
||||
cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; |
||||
|
||||
if (cfg_rcw_src == 0x25) |
||||
printf("vBank %d\n", CPLD_READ(vbank)); |
||||
else if (cfg_rcw_src == 0x106) |
||||
puts("NAND\n"); |
||||
else |
||||
printf("Invalid setting of SW4\n"); |
||||
|
||||
printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), |
||||
CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); |
||||
|
||||
puts("SERDES Reference Clocks:\n"); |
||||
sd1refclk_sel = CPLD_READ(sd1refclk_sel); |
||||
printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = initdram(0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
fsl_lsch2_early_init_f(); |
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; |
||||
|
||||
/*
|
||||
* Set CCI-400 control override register to enable barrier |
||||
* transaction |
||||
*/ |
||||
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); |
||||
|
||||
#ifdef CONFIG_FSL_IFC |
||||
init_final_memctl_regs(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ENV_IS_NOWHERE |
||||
gd->env_addr = (ulong)&default_environment[0]; |
||||
#endif |
||||
|
||||
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
||||
enable_layerscape_ns_access(); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int config_board_mux(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_MISC_INIT_R) |
||||
int misc_init_r(void) |
||||
{ |
||||
config_board_mux(); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
u8 flash_read8(void *addr) |
||||
{ |
||||
return __raw_readb(addr + 1); |
||||
} |
||||
|
||||
void flash_write16(u16 val, void *addr) |
||||
{ |
||||
u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); |
||||
|
||||
__raw_writew(shftval, addr); |
||||
} |
||||
|
||||
u16 flash_read16(void *addr) |
||||
{ |
||||
u16 val = __raw_readw(addr); |
||||
|
||||
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); |
||||
} |
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1043ARDB=y |
||||
CONFIG_FSL_LAYERSCAPE=y |
||||
@ -0,0 +1,172 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __LS1043A_COMMON_H |
||||
#define __LS1043A_COMMON_H |
||||
|
||||
#define CONFIG_REMAKE_ELF |
||||
#define CONFIG_FSL_LAYERSCAPE |
||||
#define CONFIG_FSL_LSCH2 |
||||
#define CONFIG_LS1043A |
||||
#define CONFIG_SYS_FSL_CLK |
||||
#define CONFIG_GICV2 |
||||
|
||||
#include <asm/arch/config.h> |
||||
#ifdef CONFIG_SYS_FSL_SRDS_1 |
||||
#define CONFIG_SYS_HAS_SERDES |
||||
#endif |
||||
|
||||
/* Link Definitions */ |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) |
||||
|
||||
#define CONFIG_SUPPORT_RAW_INITRD |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 |
||||
|
||||
/* Flat Device Tree Definitions */ |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
||||
|
||||
#ifndef CONFIG_SYS_FSL_DDR4 |
||||
#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ |
||||
#endif |
||||
|
||||
#define CONFIG_VERY_BIG_RAM |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 |
||||
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||
|
||||
/* Generic Timer Definitions */ |
||||
#define COUNTER_FREQUENCY 25000000 /* 25MHz */ |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/* IFC */ |
||||
#define CONFIG_FSL_IFC |
||||
/*
|
||||
* CONFIG_SYS_FLASH_BASE has the final address (core view) |
||||
* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) |
||||
* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address |
||||
* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0x60000000 |
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 |
||||
|
||||
#ifndef CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
#define CONFIG_SYS_FLASH_QUIET_TEST |
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_MXC_I2C1 |
||||
#define CONFIG_SYS_I2C_MXC_I2C2 |
||||
#define CONFIG_SYS_I2C_MXC_I2C3 |
||||
#define CONFIG_SYS_I2C_MXC_I2C4 |
||||
|
||||
/* PCIe */ |
||||
#define CONFIG_PCI /* Enable PCI/PCIE */ |
||||
#define CONFIG_PCIE1 /* PCIE controller 1 */ |
||||
#define CONFIG_PCIE2 /* PCIE controller 2 */ |
||||
#define CONFIG_PCIE3 /* PCIE controller 3 */ |
||||
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
||||
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" |
||||
|
||||
#define CONFIG_SYS_PCI_64BIT |
||||
|
||||
#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 |
||||
#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ |
||||
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 |
||||
#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ |
||||
|
||||
#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 |
||||
#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 |
||||
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 |
||||
#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP |
||||
#define CONFIG_E1000 |
||||
#define CONFIG_PCI_SCAN_SHOW |
||||
#define CONFIG_CMD_PCI |
||||
#endif |
||||
|
||||
/* Command line configuration */ |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_PING |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) |
||||
#define CONFIG_ARCH_EARLY_INIT_R |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
#define CONFIG_HWCONFIG |
||||
#define HWCONFIG_BUFFER_SIZE 128 |
||||
|
||||
/* Initial environment variables */ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
"loadaddr=0x80100000\0" \
|
||||
"kernel_addr=0x100000\0" \
|
||||
"ramdisk_addr=0x800000\0" \
|
||||
"ramdisk_size=0x2000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"kernel_start=0x61200000\0" \
|
||||
"kernel_load=0x807f0000\0" \
|
||||
"kernel_size=0x1000000\0" \
|
||||
"console=ttyAMA0,38400n8\0" |
||||
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ |
||||
"earlycon=uart8250,0x21c0500,115200" |
||||
#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ |
||||
"$kernel_size && bootm $kernel_load" |
||||
#define CONFIG_BOOTDELAY 10 |
||||
|
||||
/* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PROMPT "=> " |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_MAXARGS 64 /* max command args */ |
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
||||
|
||||
#endif /* __LS1043A_COMMON_H */ |
||||
@ -0,0 +1,191 @@ |
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __LS1043ARDB_H__ |
||||
#define __LS1043ARDB_H__ |
||||
|
||||
#include "ls1043a_common.h" |
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x60100000 |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000 |
||||
#define CONFIG_DDR_CLK_FREQ 100000000 |
||||
|
||||
#define CONFIG_LAYERSCAPE_NS_ACCESS |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||
/* Physical Memory Map */ |
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 |
||||
|
||||
#define CONFIG_FSL_DDR_BIST |
||||
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
||||
#define CONFIG_SYS_DDR_RAW_TIMING |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
||||
|
||||
/*
|
||||
* NOR Flash Definitions |
||||
*/ |
||||
#define CONFIG_SYS_NOR_CSPR_EXT (0x0) |
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
||||
#define CONFIG_SYS_NOR_CSPR \ |
||||
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
|
||||
/* NOR Flash Timing Params */ |
||||
#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
||||
CSOR_NOR_TRHZ_80) |
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ |
||||
FTIM0_NOR_TEADC(0x1) | \
|
||||
FTIM0_NOR_TAVDS(0x0) | \
|
||||
FTIM0_NOR_TEAHC(0xc)) |
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ |
||||
FTIM1_NOR_TRAD_NOR(0xb) | \
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x9)) |
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ |
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x8) | \
|
||||
FTIM2_NOR_TWP(0x10)) |
||||
#define CONFIG_SYS_NOR_FTIM3 0 |
||||
#define CONFIG_SYS_IFC_CCR 0x01000000 |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } |
||||
|
||||
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
||||
#define CONFIG_SYS_WRITE_SWAPPED_DATA |
||||
|
||||
/*
|
||||
* NAND Flash Definitions |
||||
*/ |
||||
#define CONFIG_NAND_FSL_IFC |
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0x7e800000 |
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_NAND \
|
||||
| CSPR_V) |
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
|
||||
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */ |
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ |
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x7) | \
|
||||
FTIM0_NAND_TWH(0xa)) |
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0xe) | \
|
||||
FTIM1_NAND_TRP(0x18)) |
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ |
||||
FTIM2_NAND_TREH(0xa) | \
|
||||
FTIM2_NAND_TWHRE(0x1e)) |
||||
#define CONFIG_SYS_NAND_FTIM3 0x0 |
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_CMD_NAND |
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
||||
|
||||
/*
|
||||
* CPLD |
||||
*/ |
||||
#define CONFIG_SYS_CPLD_BASE 0x7fb00000 |
||||
#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE |
||||
|
||||
#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) |
||||
#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ |
||||
CSPR_PORT_SIZE_8 | \
|
||||
CSPR_MSEL_GPCM | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) |
||||
#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
||||
CSOR_NOR_NOR_MODE_AVD_NOR | \
|
||||
CSOR_NOR_TRHZ_80) |
||||
|
||||
/* CPLD Timing parameters for IFC GPCM */ |
||||
#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ |
||||
FTIM0_GPCM_TEADC(0xf) | \
|
||||
FTIM0_GPCM_TEAHC(0xf)) |
||||
#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
||||
FTIM1_GPCM_TRAD(0x3f)) |
||||
#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
||||
FTIM2_GPCM_TCH(0xf) | \
|
||||
FTIM2_GPCM_TWP(0xff)) |
||||
#define CONFIG_SYS_CPLD_FTIM3 0x0 |
||||
|
||||
/* IFC Timing Params */ |
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||
|
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR |
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK |
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR |
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 |
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 |
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 |
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 |
||||
|
||||
/* EEPROM */ |
||||
#define CONFIG_ID_EEPROM |
||||
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 |
||||
#define CONFIG_ENV_SIZE 0x20000 |
||||
|
||||
#endif /* __LS1043ARDB_H__ */ |
||||
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Reference in new issue