Tom Rini
8 years ago
commit
f3c264f9de
@ -0,0 +1,163 @@ |
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/*
|
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/acpi_table.h> |
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#include <asm/ioapic.h> |
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#include <asm/mpspec.h> |
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#include <asm/tables.h> |
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#include <asm/arch/iomap.h> |
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|
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void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, |
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void *dsdt) |
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{ |
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struct acpi_table_header *header = &(fadt->header); |
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u16 pmbase = ACPI_PM1_BASE_ADDRESS; |
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memset((void *)fadt, 0, sizeof(struct acpi_fadt)); |
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acpi_fill_header(header, "FACP"); |
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header->length = sizeof(struct acpi_fadt); |
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header->revision = 4; |
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fadt->firmware_ctrl = (u32)facs; |
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fadt->dsdt = (u32)dsdt; |
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fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED; |
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fadt->sci_int = 9; |
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fadt->smi_cmd = 0; |
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fadt->acpi_enable = 0; |
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fadt->acpi_disable = 0; |
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fadt->s4bios_req = 0; |
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fadt->pstate_cnt = 0; |
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fadt->pm1a_evt_blk = pmbase; |
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fadt->pm1b_evt_blk = 0x0; |
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fadt->pm1a_cnt_blk = pmbase + 0x4; |
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fadt->pm1b_cnt_blk = 0x0; |
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fadt->pm2_cnt_blk = 0x0; |
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fadt->pm_tmr_blk = pmbase + 0x8; |
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fadt->gpe0_blk = ACPI_GPE0_BASE_ADDRESS; |
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fadt->gpe1_blk = 0; |
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fadt->pm1_evt_len = 4; |
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fadt->pm1_cnt_len = 2; |
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fadt->pm2_cnt_len = 0; |
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fadt->pm_tmr_len = 4; |
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fadt->gpe0_blk_len = 8; |
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fadt->gpe1_blk_len = 0; |
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fadt->gpe1_base = 0; |
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fadt->cst_cnt = 0; |
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
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fadt->flush_size = 0; |
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fadt->flush_stride = 0; |
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fadt->duty_offset = 1; |
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fadt->duty_width = 3; |
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fadt->day_alrm = 0x00; |
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fadt->mon_alrm = 0x00; |
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fadt->century = 0x00; |
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; |
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fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
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ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON | |
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ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER | |
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ACPI_FADT_PLATFORM_CLOCK; |
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fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->reset_reg.bit_width = 8; |
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fadt->reset_reg.bit_offset = 0; |
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
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fadt->reset_reg.addrl = IO_PORT_RESET; |
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fadt->reset_reg.addrh = 0; |
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fadt->reset_value = SYS_RST | RST_CPU; |
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fadt->x_firmware_ctl_l = (u32)facs; |
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fadt->x_firmware_ctl_h = 0; |
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fadt->x_dsdt_l = (u32)dsdt; |
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fadt->x_dsdt_h = 0; |
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
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fadt->x_pm1a_evt_blk.bit_offset = 0; |
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
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fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; |
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fadt->x_pm1a_evt_blk.addrh = 0x0; |
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fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm1b_evt_blk.bit_width = 0; |
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fadt->x_pm1b_evt_blk.bit_offset = 0; |
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fadt->x_pm1b_evt_blk.access_size = 0; |
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fadt->x_pm1b_evt_blk.addrl = 0x0; |
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fadt->x_pm1b_evt_blk.addrh = 0x0; |
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
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fadt->x_pm1a_cnt_blk.bit_offset = 0; |
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
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fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; |
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fadt->x_pm1a_cnt_blk.addrh = 0x0; |
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fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm1b_cnt_blk.bit_width = 0; |
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fadt->x_pm1b_cnt_blk.bit_offset = 0; |
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fadt->x_pm1b_cnt_blk.access_size = 0; |
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fadt->x_pm1b_cnt_blk.addrl = 0x0; |
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fadt->x_pm1b_cnt_blk.addrh = 0x0; |
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fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; |
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fadt->x_pm2_cnt_blk.bit_offset = 0; |
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
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fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; |
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fadt->x_pm2_cnt_blk.addrh = 0x0; |
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
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fadt->x_pm_tmr_blk.bit_offset = 0; |
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
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fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; |
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fadt->x_pm_tmr_blk.addrh = 0x0; |
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; |
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fadt->x_gpe0_blk.bit_offset = 0; |
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; |
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fadt->x_gpe0_blk.addrh = 0x0; |
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fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_gpe1_blk.bit_width = 0; |
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fadt->x_gpe1_blk.bit_offset = 0; |
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fadt->x_gpe1_blk.access_size = 0; |
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fadt->x_gpe1_blk.addrl = 0x0; |
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fadt->x_gpe1_blk.addrh = 0x0; |
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header->checksum = table_compute_checksum(fadt, header->length); |
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} |
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static int acpi_create_madt_irq_overrides(u32 current) |
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{ |
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struct acpi_madt_irqoverride *irqovr; |
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u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; |
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int length = 0; |
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irqovr = (void *)current; |
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length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); |
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irqovr = (void *)(current + length); |
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length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags); |
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return length; |
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} |
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u32 acpi_fill_madt(u32 current) |
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{ |
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current += acpi_create_madt_lapics(current); |
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current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, |
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io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0); |
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current += acpi_create_madt_irq_overrides(current); |
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return current; |
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} |
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@ -0,0 +1,15 @@ |
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/device.h> |
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#define PCI_DEV_PIRQ_ROUTES \ |
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PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D) |
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#define PCIE_BRIDGE_IRQ_ROUTES \ |
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PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D) |
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@ -0,0 +1,125 @@ |
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/* |
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/* Intel LPC Bus Device - 0:1f.0 */ |
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Device (LPCB) |
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{ |
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Name(_ADR, 0x001f0000) |
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OperationRegion(PRTX, PCI_Config, 0x60, 8) |
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Field(PRTX, AnyAcc, NoLock, Preserve) { |
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PRTA, 8, |
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PRTB, 8, |
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PRTC, 8, |
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PRTD, 8, |
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PRTE, 8, |
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PRTF, 8, |
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PRTG, 8, |
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PRTH, 8, |
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} |
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#include <asm/acpi/irqlinks.asl> |
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/* Firmware Hub */ |
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Device (FWH) |
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{ |
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Name(_HID, EISAID("INT0800")) |
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Name(_CRS, ResourceTemplate() |
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{ |
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Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) |
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}) |
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} |
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/* 8259 Interrupt Controller */ |
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Device (PIC) |
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{ |
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Name(_HID, EISAID("PNP0000")) |
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Name(_CRS, ResourceTemplate() |
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{ |
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IO(Decode16, 0x20, 0x20, 0x01, 0x02) |
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IO(Decode16, 0x24, 0x24, 0x01, 0x02) |
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IO(Decode16, 0x28, 0x28, 0x01, 0x02) |
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IO(Decode16, 0x2c, 0x2c, 0x01, 0x02) |
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IO(Decode16, 0x30, 0x30, 0x01, 0x02) |
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IO(Decode16, 0x34, 0x34, 0x01, 0x02) |
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IO(Decode16, 0x38, 0x38, 0x01, 0x02) |
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IO(Decode16, 0x3c, 0x3c, 0x01, 0x02) |
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IO(Decode16, 0xa0, 0xa0, 0x01, 0x02) |
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IO(Decode16, 0xa4, 0xa4, 0x01, 0x02) |
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IO(Decode16, 0xa8, 0xa8, 0x01, 0x02) |
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IO(Decode16, 0xac, 0xac, 0x01, 0x02) |
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IO(Decode16, 0xb0, 0xb0, 0x01, 0x02) |
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IO(Decode16, 0xb4, 0xb4, 0x01, 0x02) |
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IO(Decode16, 0xb8, 0xb8, 0x01, 0x02) |
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IO(Decode16, 0xbc, 0xbc, 0x01, 0x02) |
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IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02) |
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IRQNoFlags () { 2 } |
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}) |
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} |
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/* 8254 timer */ |
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Device (TIMR) |
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{ |
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Name(_HID, EISAID("PNP0100")) |
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Name(_CRS, ResourceTemplate() |
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{ |
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IO(Decode16, 0x40, 0x40, 0x01, 0x04) |
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IO(Decode16, 0x50, 0x50, 0x10, 0x04) |
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IRQNoFlags() { 0 } |
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}) |
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} |
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/* HPET */ |
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Device (HPET) |
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{ |
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Name(_HID, EISAID("PNP0103")) |
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Name(_CID, 0x010CD041) |
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Name(_CRS, ResourceTemplate() |
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{ |
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Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE) |
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}) |
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Method(_STA) |
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{ |
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Return (STA_VISIBLE) |
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} |
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} |
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/* Real Time Clock */ |
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Device (RTC) |
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{ |
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Name(_HID, EISAID("PNP0B00")) |
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Name(_CRS, ResourceTemplate() |
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{ |
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IO(Decode16, 0x70, 0x70, 1, 8) |
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IRQNoFlags() { 8 } |
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}) |
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} |
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/* LPC device: Resource consumption */ |
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Device (LDRC) |
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{ |
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Name(_HID, EISAID("PNP0C02")) |
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Name(_UID, 2) |
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Name(RBUF, ResourceTemplate() |
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{ |
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IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */ |
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IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */ |
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IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */ |
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IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */ |
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IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ |
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IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ |
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IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ |
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}) |
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Method(_CRS, 0, NotSerialized) |
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{ |
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Return (RBUF) |
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} |
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} |
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} |
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@ -0,0 +1,33 @@ |
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/* |
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/acpi/statdef.asl> |
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#include <asm/arch/iomap.h> |
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#include <asm/arch/irq.h> |
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/* |
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* The _PTS method (Prepare To Sleep) is called before the OS is |
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* entering a sleep state. The sleep state number is passed in Arg0. |
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*/ |
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Method(_PTS, 1) |
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{ |
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} |
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/* The _WAK method is called on system wakeup */ |
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Method(_WAK, 1) |
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{ |
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Return (Package() {0, 0}) |
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} |
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/* TODO: add CPU ASL support */ |
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Scope (\_SB) |
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{ |
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#include "southcluster.asl" |
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} |
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/* Chipset specific sleep states */ |
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#include "sleepstates.asl" |
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@ -0,0 +1,10 @@ |
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/* |
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) |
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Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) |
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Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) |
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Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) |
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@ -0,0 +1,184 @@ |
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/* |
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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Device (PCI0) |
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{ |
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Name(_HID, EISAID("PNP0A08")) /* PCIe */ |
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Name(_CID, EISAID("PNP0A03")) /* PCI */ |
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Name(_ADR, 0) |
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Name(_BBN, 0) |
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Name(MCRS, ResourceTemplate() |
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{ |
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/* Bus Numbers */ |
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WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, |
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00) |
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|
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/* IO Region 0 */ |
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00) |
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|
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/* PCI Config Space */ |
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IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
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|
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/* IO Region 1 */ |
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01) |
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|
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/* VGA memory (0xa0000-0xbffff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
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0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
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0x00020000, , , ASEG) |
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|
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/* OPROM reserved (0xc0000-0xc3fff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
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0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
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0x00004000, , , OPR0) |
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|
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/* OPROM reserved (0xc4000-0xc7fff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
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0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
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0x00004000, , , OPR1) |
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|
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/* OPROM reserved (0xc8000-0xcbfff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
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0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
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0x00004000, , , OPR2) |
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|
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/* OPROM reserved (0xcc000-0xcffff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
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0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
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0x00004000, , , OPR3) |
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|
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/* OPROM reserved (0xd0000-0xd3fff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
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0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
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0x00004000, , , OPR4) |
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|
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/* OPROM reserved (0xd4000-0xd7fff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
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0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
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0x00004000, , , OPR5) |
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|
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/* OPROM reserved (0xd8000-0xdbfff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
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0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
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0x00004000, , , OPR6) |
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|
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/* OPROM reserved (0xdc000-0xdffff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
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0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
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0x00004000, , , OPR7) |
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|
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/* BIOS Extension (0xe0000-0xe3fff) */ |
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
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Cacheable, ReadWrite, |
||||
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
||||
0x00004000, , , ESG0) |
||||
|
||||
/* BIOS Extension (0xe4000-0xe7fff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
||||
0x00004000, , , ESG1) |
||||
|
||||
/* BIOS Extension (0xe8000-0xebfff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
||||
0x00004000, , , ESG2) |
||||
|
||||
/* BIOS Extension (0xec000-0xeffff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
||||
0x00004000, , , ESG3) |
||||
|
||||
/* System BIOS (0xf0000-0xfffff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
||||
0x00010000, , , FSEG) |
||||
|
||||
/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, |
||||
0x00000000, , , PMEM) |
||||
}) |
||||
|
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
/* Update PCI resource area */ |
||||
CreateDwordField(MCRS, ^PMEM._MIN, PMIN) |
||||
CreateDwordField(MCRS, ^PMEM._MAX, PMAX) |
||||
CreateDwordField(MCRS, ^PMEM._LEN, PLEN) |
||||
|
||||
/* |
||||
* Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h) |
||||
* |
||||
* TODO: for generic usage, read TOLM value from register, or |
||||
* from global NVS (not implemented by U-Boot yet). |
||||
*/ |
||||
Store(0x80000000, PMIN) |
||||
Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX) |
||||
Add(Subtract(PMAX, PMIN), 1, PLEN) |
||||
|
||||
Return (MCRS) |
||||
} |
||||
|
||||
/* Device Resource Consumption */ |
||||
Device (PDRC) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C02")) |
||||
Name(_UID, 1) |
||||
|
||||
Name(PDRS, ResourceTemplate() { |
||||
Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000) |
||||
Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) |
||||
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) |
||||
IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE) |
||||
IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE) |
||||
IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE) |
||||
}) |
||||
|
||||
/* Current Resource Settings */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Return (PDRS) |
||||
} |
||||
} |
||||
|
||||
Method(_OSC, 4) |
||||
{ |
||||
/* Check for proper GUID */ |
||||
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { |
||||
/* Let OS control everything */ |
||||
Return (Arg3) |
||||
} Else { |
||||
/* Unrecognized UUID */ |
||||
CreateDWordField(Arg3, 0, CDW1) |
||||
Or(CDW1, 4, CDW1) |
||||
Return (Arg3) |
||||
} |
||||
} |
||||
|
||||
/* LPC Bridge 0:1f.0 */ |
||||
#include "lpc.asl" |
||||
|
||||
/* IRQ routing for each PCI device */ |
||||
#include <asm/acpi/irqroute.asl> |
||||
} |
||||
@ -0,0 +1,47 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _QUARK_IOMAP_H_ |
||||
#define _QUARK_IOMAP_H_ |
||||
|
||||
/* Memory Mapped IO bases */ |
||||
|
||||
/* ESRAM */ |
||||
#define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE |
||||
#define ESRAM_BASE_SIZE ESRAM_SIZE |
||||
|
||||
/* PCI Configuration Space */ |
||||
#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE |
||||
#define MCFG_BASE_SIZE 0x10000000 |
||||
|
||||
/* High Performance Event Timer */ |
||||
#define HPET_BASE_ADDRESS 0xfed00000 |
||||
#define HPET_BASE_SIZE 0x400 |
||||
|
||||
/* Root Complex Base Address */ |
||||
#define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE |
||||
#define RCBA_BASE_SIZE 0x4000 |
||||
|
||||
/* IO Port bases */ |
||||
#define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE |
||||
#define ACPI_PM1_BASE_SIZE 0x10 |
||||
|
||||
#define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE |
||||
#define ACPI_PBLK_BASE_SIZE 0x10 |
||||
|
||||
#define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE |
||||
#define SPI_DMA_BASE_SIZE 0x10 |
||||
|
||||
#define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE |
||||
#define GPIO_BASE_SIZE 0x80 |
||||
|
||||
#define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE |
||||
#define ACPI_GPE0_BASE_SIZE 0x40 |
||||
|
||||
#define WDT_BASE_ADDRESS CONFIG_WDT_BASE |
||||
#define WDT_BASE_SIZE 0x40 |
||||
|
||||
#endif /* _QUARK_IOMAP_H_ */ |
||||
@ -0,0 +1,19 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _QUARK_IRQ_H_ |
||||
#define _QUARK_IRQ_H_ |
||||
|
||||
#define PIRQA_APIC_IRQ 16 |
||||
#define PIRQB_APIC_IRQ 17 |
||||
#define PIRQC_APIC_IRQ 18 |
||||
#define PIRQD_APIC_IRQ 19 |
||||
#define PIRQE_APIC_IRQ 20 |
||||
#define PIRQF_APIC_IRQ 21 |
||||
#define PIRQG_APIC_IRQ 22 |
||||
#define PIRQH_APIC_IRQ 23 |
||||
|
||||
#endif /* _QUARK_IRQ_H_ */ |
||||
@ -0,0 +1,3 @@ |
||||
dsdt.aml |
||||
dsdt.asl.tmp |
||||
dsdt.c |
||||
@ -0,0 +1,11 @@ |
||||
/* |
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* Power Button */ |
||||
Device (PWRB) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0C")) |
||||
} |
||||
@ -0,0 +1,14 @@ |
||||
/* |
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) |
||||
{ |
||||
/* platform specific */ |
||||
#include <asm/arch/acpi/platform.asl> |
||||
|
||||
/* board specific */ |
||||
#include "acpi/mainboard.asl" |
||||
} |
||||
Loading…
Reference in new issue