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@ -21,10 +21,6 @@ |
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#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ |
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/* Some clock/baud constants */ |
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#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ |
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#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ |
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struct uart_zynq { |
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u32 control; /* Control Register [8:0] */ |
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u32 mode; /* Mode Register [10:0] */ |
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