Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'

Browse Source
master
Albert ARIBAUD 11 years ago
parent d51a2a2d63 b8f383b86b
commit f4e4aadead
5 changed files with 269 additions and 17 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 83
      board/renesas/koelsch/koelsch.c
  2. 78
      board/renesas/lager/lager.c
  3. 49
      doc/README.rmobile
  4. 41
      include/configs/koelsch.h
  5. 35
      include/configs/lager.h

83
board/renesas/koelsch/koelsch.c
Unescape View File

@ -16,6 +16,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include "qos.h"
@ -207,6 +209,10 @@ void s_init(void)
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define PMMR 0xE6060000
#define GPSR4 0xE6060014
#define IPSR14 0xE6060058
@ -241,9 +247,16 @@ int board_early_init_f(void)
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
return 0;
}
/* LSI pin pull-up control */
#define PUPR5 0xe6060114
#define PUPR5_ETH 0x3FFC0000
#define PUPR5_ETH_MAGIC (1 << 27)
int board_init(void)
{
/* adress of boot parameters */
@ -252,9 +265,59 @@ int board_init(void)
/* Init PFC controller */
r8a7791_pinmux_init();
/* ETHER Enable */
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
gpio_request(GPIO_FN_ETH_RXD0, NULL);
gpio_request(GPIO_FN_ETH_RXD1, NULL);
gpio_request(GPIO_FN_ETH_LINK, NULL);
gpio_request(GPIO_FN_ETH_REFCLK, NULL);
gpio_request(GPIO_FN_ETH_MDIO, NULL);
gpio_request(GPIO_FN_ETH_TXD1, NULL);
gpio_request(GPIO_FN_ETH_TX_EN, NULL);
gpio_request(GPIO_FN_ETH_TXD0, NULL);
gpio_request(GPIO_FN_ETH_MDC, NULL);
gpio_request(GPIO_FN_IRQ0, NULL);
mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
gpio_direction_output(GPIO_GP_5_22, 0);
mdelay(20);
gpio_set_value(GPIO_GP_5_22, 1);
udelay(1);
return 0;
}
#define CXR24 0xEE7003C0 /* MAC address high register */
#define CXR25 0xEE7003C8 /* MAC address low register */
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SH_ETHER
int ret = -ENODEV;
u32 val;
unsigned char enetaddr[6];
ret = sh_eth_initialize(bis);
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
return ret;
/* Set Mac address */
val = enetaddr[0] << 24 | enetaddr[1] << 16 |
enetaddr[2] << 8 | enetaddr[3];
writel(val, CXR24);
val = enetaddr[4] << 8 | enetaddr[5];
writel(val, CXR25);
return ret;
#else
return 0;
#endif
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
@ -263,6 +326,20 @@ int dram_init(void)
return 0;
}
/* koelsch has KSZ8041NL/RNL */
#define PHY_CONTROL1 0x1E
#define PHY_LED_MODE 0xC0000
#define PHY_LED_MODE_ACK 0x4000
int board_phy_config(struct phy_device *phydev)
{
int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
ret &= ~PHY_LED_MODE;
ret |= PHY_LED_MODE_ACK;
ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
};
@ -280,4 +357,10 @@ int board_late_init(void)
void reset_cpu(ulong addr)
{
u8 val;
i2c_set_bus_num(2); /* PowerIC connected to ch2 */
i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}

78
board/renesas/lager/lager.c
Unescape View File

@ -18,6 +18,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <miiphy.h>
#include <i2c.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
@ -207,6 +209,10 @@ void s_init(void)
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define PMMR 0xE6060000
#define GPSR4 0xE6060014
#define IPSR14 0xE6060058
@ -242,6 +248,9 @@ int board_early_init_f(void)
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
return 0;
}
@ -256,6 +265,68 @@ int board_init(void)
/* Init PFC controller */
r8a7790_pinmux_init();
/* ETHER Enable */
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
gpio_request(GPIO_FN_ETH_RXD0, NULL);
gpio_request(GPIO_FN_ETH_RXD1, NULL);
gpio_request(GPIO_FN_ETH_LINK, NULL);
gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
gpio_request(GPIO_FN_ETH_MDIO, NULL);
gpio_request(GPIO_FN_ETH_TXD1, NULL);
gpio_request(GPIO_FN_ETH_TX_EN, NULL);
gpio_request(GPIO_FN_ETH_MAGIC, NULL);
gpio_request(GPIO_FN_ETH_TXD0, NULL);
gpio_request(GPIO_FN_ETH_MDC, NULL);
gpio_request(GPIO_FN_IRQ0, NULL);
gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */
gpio_direction_output(GPIO_GP_5_31, 0);
mdelay(20);
gpio_set_value(GPIO_GP_5_31, 1);
udelay(1);
return 0;
}
#define CXR24 0xEE7003C0 /* MAC address high register */
#define CXR25 0xEE7003C8 /* MAC address low register */
int board_eth_init(bd_t *bis)
{
int ret = -ENODEV;
#ifdef CONFIG_SH_ETHER
u32 val;
unsigned char enetaddr[6];
ret = sh_eth_initialize(bis);
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
return ret;
/* Set Mac address */
val = enetaddr[0] << 24 | enetaddr[1] << 16 |
enetaddr[2] << 8 | enetaddr[3];
writel(val, CXR24);
val = enetaddr[4] << 8 | enetaddr[5];
writel(val, CXR25);
#endif
return ret;
}
/* lager has KSZ8041NL/RNL */
#define PHY_CONTROL1 0x1E
#define PHY_LED_MODE 0xC0000
#define PHY_LED_MODE_ACK 0x4000
int board_phy_config(struct phy_device *phydev)
{
int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
ret &= ~PHY_LED_MODE;
ret |= PHY_LED_MODE_ACK;
ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
return 0;
}
@ -284,4 +355,11 @@ int board_late_init(void)
void reset_cpu(ulong addr)
{
u8 val;
i2c_set_bus_num(3); /* PowerIC connected to ch3 */
i2c_init(400000, 0);
i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}

49
doc/README.rmobile
Unescape View File

@ -2,13 +2,15 @@ Summary
=======
This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9.
and R-Car[2]family of SoCs. Renesas's RMOBILE/R-Car SoC family contains an ARM
Cortex-A9.
Currently the following boards are supported:
* KMC KZM-A9-GT [2]
* Atmark-Techno Armadillo-800-EVA [3]
* KMC KZM-A9-GT [3]
* Atmark-Techno Armadillo-800-EVA [4]
* Renesas Electronics Lager
* Renesas Electronics Koelsch
Toolchain
=========
@ -17,7 +19,7 @@ ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a).
But currently we compile with -march=armv5 to allow more compilers to work.
(For U-Boot code this has no performance impact.)
Because there was no compiler which is supporting armv7a not much before.
Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a
Currently, ELDK[5], Linaro[6], CodeSourcey[7] and Emdebian[8] supports -march=armv7a
and you can get.
Build
@ -25,13 +27,26 @@ Build
* KZM-A9-GT
make kzm9g_config
make
make kzm9g_config
make
* Armadillo-800-EVA
make armadillo-800eva_config
make
make armadillo-800eva_config
make
Note: Armadillo-800-EVA's U-Boot supports booting from SDcard only.
Please see "B.2 Appendix B Boot Specifications" in hardware manual.
* Lager
make lager_config
make
* Koelsch
make koelsch_config
make
Links
=====
@ -40,26 +55,30 @@ Links
http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp
[2] KZM-A9-GT
[2] Renesas R-Car:
http://am.renesas.com/products/soc/assp/automotive/index.jsp
[3] KZM-A9-GT
http://www.kmckk.co.jp/kzma9-gt/index.html
[3] Armadillo-800-EVA
[4] Armadillo-800-EVA
http://armadillo.atmark-techno.com/armadillo-800-EVA
[4] ELDK
[5] ELDK
http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6.
[5] Linaro
[6] Linaro
http://www.linaro.org/downloads/
[6] CodeSourcey
[7] CodeSourcey
http://www.mentor.com/embedded-software/codesourcery
[7] Emdebian
[8] Emdebian
http://www.emdebian.org/crosstools.html

41
include/configs/koelsch.h
Unescape View File

@ -18,13 +18,18 @@
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_EDITENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_EDITENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_RUN
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_FLASH
@ -123,6 +128,20 @@
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
/* SH Ether */
#define CONFIG_NET_MULTI
#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 10000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
@ -130,4 +149,22 @@
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
/* i2c */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000
#define CONFIG_SYS_I2C_SH_SPEED0 400000
#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000
#define CONFIG_SYS_I2C_SH_SPEED1 400000
#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
#define CONFIG_SYS_I2C_SH_SPEED2 400000
#define CONFIG_SH_I2C_DATA_HIGH 4
#define CONFIG_SH_I2C_DATA_LOW 5
#define CONFIG_SH_I2C_CLOCK 10000000
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
#endif /* __KOELSCH_H */

35
include/configs/lager.h
Unescape View File

@ -28,6 +28,11 @@
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_RUN
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_FLASH
@ -127,12 +132,42 @@
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
/* SH Ether */
#define CONFIG_NET_MULTI
#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_RCAR
#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000
#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000
#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000
#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000
#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* Board Clock */
#define CONFIG_BASE_CLK_FREQ 20000000u
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2)
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4

Write Preview
Loading…
Cancel
Save