wdenk
21 years ago
parent
68ce8957e5
commit
f5300ab241
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/*
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* (C) Copyright 2003 |
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* Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de> |
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* |
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* Based on cpu/arm920t/serial.c, by Gary Jennejohn |
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* (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <s3c2400.h> |
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#include "rs485.h" |
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static void rs485_setbrg (void); |
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static void rs485_cfgio (void); |
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static void set_rs485re(unsigned char rs485re_state); |
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static void set_rs485de(unsigned char rs485de_state); |
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static void rs485_setbrg (void); |
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#ifdef NOT_USED |
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static void trab_rs485_disable_tx(void); |
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static void trab_rs485_disable_rx(void); |
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#endif |
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#define UART_NR S3C24X0_UART1 |
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/* CPLD-Register for controlling TRAB hardware functions */ |
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#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) |
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static void rs485_setbrg (void) |
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{ |
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S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); |
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int i; |
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unsigned int reg = 0; |
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/* value is calculated so : (int)(PCLK/16./baudrate) -1 */ |
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/* reg = (33000000 / (16 * gd->baudrate)) - 1; */ |
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reg = (33000000 / (16 * 38.400)) - 1; |
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/* FIFO enable, Tx/Rx FIFO clear */ |
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uart->UFCON = 0x07; |
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uart->UMCON = 0x0; |
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/* Normal,No parity,1 stop,8 bit */ |
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uart->ULCON = 0x3; |
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/*
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* tx=level,rx=edge,disable timeout int.,enable rx error int., |
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* normal,interrupt or polling |
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*/ |
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uart->UCON = 0x245; |
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uart->UBRDIV = reg; |
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for (i = 0; i < 100; i++); |
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} |
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static void rs485_cfgio (void) |
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{ |
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S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
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gpio->PFCON &= ~(0x3 << 2); |
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gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */ |
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gpio->PFCON &= ~(0x3 << 6); |
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gpio->PFCON |= (0x2 << 6); /* configure GPF3 as TXD1 */ |
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gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */ |
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gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */ |
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gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */ |
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} |
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/*
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* Initialise the rs485 port with the given baudrate. The settings |
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* are always 8 data bits, no parity, 1 stop bit, no start bits. |
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* |
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*/ |
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int rs485_init (void) |
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{ |
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rs485_cfgio (); |
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rs485_setbrg (); |
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return (0); |
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} |
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/*
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* Read a single byte from the rs485 port. Returns 1 on success, 0 |
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* otherwise. When the function is succesfull, the character read is |
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* written into its argument c. |
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*/ |
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int rs485_getc (void) |
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{ |
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S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); |
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/* wait for character to arrive */ |
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while (!(uart->UTRSTAT & 0x1)); |
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return uart->URXH & 0xff; |
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} |
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/*
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* Output a single byte to the rs485 port. |
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*/ |
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void rs485_putc (const char c) |
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{ |
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S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); |
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/* wait for room in the tx FIFO */ |
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while (!(uart->UTRSTAT & 0x2)); |
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uart->UTXH = c; |
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/* If \n, also do \r */ |
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if (c == '\n') |
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rs485_putc ('\r'); |
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} |
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/*
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* Test whether a character is in the RX buffer |
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*/ |
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int rs485_tstc (void) |
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{ |
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S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); |
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return uart->UTRSTAT & 0x1; |
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} |
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void rs485_puts (const char *s) |
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{ |
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while (*s) { |
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rs485_putc (*s++); |
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} |
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} |
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/*
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* State table: |
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* RE DE Result |
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* 1 1 XMIT |
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* 0 0 RCV |
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* 1 0 Shutdown |
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*/ |
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/* function that controls the receiver enable for the rs485 */ |
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/* rs485re_state reflects the level (0/1) of the RE pin */ |
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static void set_rs485re(unsigned char rs485re_state) |
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{ |
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if(rs485re_state) |
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*CPLD_RS485_RE = 0x010000; |
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else |
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*CPLD_RS485_RE = 0x0; |
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} |
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/* function that controls the sender enable for the rs485 */ |
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/* rs485de_state reflects the level (0/1) of the DE pin */ |
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static void set_rs485de(unsigned char rs485de_state) |
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{ |
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S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
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/* This is on PORT A bit 11 */ |
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if(rs485de_state) |
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gpio->PADAT |= (1 << 11); |
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else |
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gpio->PADAT &= ~(1 << 11); |
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} |
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void trab_rs485_enable_tx(void) |
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{ |
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set_rs485de(1); |
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set_rs485re(1); |
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} |
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void trab_rs485_enable_rx(void) |
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{ |
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set_rs485re(0); |
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set_rs485de(0); |
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} |
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#ifdef NOT_USED |
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static void trab_rs485_disable_tx(void) |
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{ |
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set_rs485de(0); |
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} |
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static void trab_rs485_disable_rx(void) |
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{ |
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set_rs485re(1); |
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} |
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#endif |
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@ -0,0 +1,37 @@ |
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/*
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* (C) Copyright 2003 |
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* Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de> |
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* |
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* Based on cpu/arm920t/serial.c, by Gary Jennejohn |
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* (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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*/ |
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#ifndef _RS485_H_ |
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#define _RS485_H_ |
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#include <s3c2400.h> |
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int rs485_init (void); |
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int rs485_getc (void); |
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void rs485_putc (const char c); |
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int rs485_tstc (void); |
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void rs485_puts (const char *s); |
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void trab_rs485_enable_tx(void); |
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void trab_rs485_enable_rx(void); |
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#endif /* _RS485_H_ */ |
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