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ARM: UniPhier: merge UniPhier config headers into a single file

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Some configurations have been moved to Kconfig and the difference
among the config headers of UniPhier SoC variants is getting smaller
and smaller.  Now is a good time to merge them into a single file.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
master
Masahiro Yamada 10 years ago
parent 3201455d6a
commit f5d0b9b2c3
5 changed files with 48 additions and 119 deletions
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  1. 4
      arch/arm/cpu/armv7/uniphier/Kconfig
  2. 38
      include/configs/ph1_ld4.h
  3. 38
      include/configs/ph1_pro4.h
  4. 40
      include/configs/ph1_sld8.h
  5. 47
      include/configs/uniphier.h

4
arch/arm/cpu/armv7/uniphier/Kconfig
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@ -5,9 +5,7 @@ config SYS_SOC
default "uniphier"
config SYS_CONFIG_NAME
default "ph1_pro4" if MACH_PH1_PRO4
default "ph1_ld4" if MACH_PH1_LD4
default "ph1_sld8" if MACH_PH1_SLD8
default "uniphier"
config UNIPHIER_SMP
bool

38
include/configs/ph1_ld4.h
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@ -1,38 +0,0 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PH1_XXX_H
#define __PH1_XXX_H
/*
* Serial Configuration
* SoC UART : enable CONFIG_UNIPHIER_SERIAL
* On-board UART: enable CONFIG_SYS_NS16550_SERIAL
*/
#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif
#define CONFIG_SMC911X
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
/*
* Memory Size & Mapping
*/
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x10000000
#define CONFIG_SDRAM1_BASE 0x90000000
#define CONFIG_SDRAM1_SIZE 0x10000000
#define CONFIG_SPL_TEXT_BASE 0x40000
#include "uniphier-common.h"
#endif /* __PH1_XXX_H */

38
include/configs/ph1_pro4.h
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@ -1,38 +0,0 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PH1_XXX_H
#define __PH1_XXX_H
/*
* Serial Configuration
* SoC UART : enable CONFIG_UNIPHIER_SERIAL
* On-board UART: enable CONFIG_SYS_NS16550_SERIAL
*/
#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif
#define CONFIG_SMC911X
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2
/*
* Memory Size & Mapping
*/
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x20000000
#define CONFIG_SDRAM1_BASE 0xa0000000
#define CONFIG_SDRAM1_SIZE 0x20000000
#define CONFIG_SPL_TEXT_BASE 0x100000
#include "uniphier-common.h"
#endif /* __PH1_XXX_H */

40
include/configs/ph1_sld8.h
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@ -1,40 +0,0 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PH1_XXX_H
#define __PH1_XXX_H
/*
* Serial Configuration
* SoC UART : enable CONFIG_UNIPHIER_SERIAL
* On-board UART: enable CONFIG_SYS_NS16550_SERIAL
*/
#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif
#define CONFIG_SMC911X
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
/* #define CONFIG_DDR_STANDARD */
/*
* Memory Size & Mapping
*/
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x10000000
#define CONFIG_SDRAM1_BASE 0x90000000
#define CONFIG_SDRAM1_SIZE 0x10000000
#define CONFIG_SPL_TEXT_BASE 0x40000
#include "uniphier-common.h"
#endif /* __PH1_XXX_H */

47
include/configs/uniphier-common.h → include/configs/uniphier.h
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@ -10,6 +10,39 @@
#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__
#if defined(CONFIG_MACH_PH1_PRO4)
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x20000000
#define CONFIG_SDRAM1_BASE 0xa0000000
#define CONFIG_SDRAM1_SIZE 0x20000000
#endif
#if defined(CONFIG_MACH_PH1_LD4)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x10000000
#define CONFIG_SDRAM1_BASE 0x90000000
#define CONFIG_SDRAM1_SIZE 0x10000000
#endif
#if defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x10000000
#define CONFIG_SDRAM1_BASE 0x90000000
#define CONFIG_SDRAM1_SIZE 0x10000000
#endif
/*
* Support card address map
*/
@ -34,6 +67,13 @@
#define CONFIG_SYS_NS16550_REG_SIZE -2
#endif
/* TODO: move to Kconfig and device tree */
#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
#define CONFIG_SMC911X_32_BIT
@ -226,6 +266,13 @@
#define CONFIG_SYS_TEXT_BASE 0x84000000
#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_SPL_TEXT_BASE 0x00040000
#endif
#if defined(CONFIG_MACH_PH1_PRO4)
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
#define CONFIG_BOARD_POSTCLK_INIT
#ifndef CONFIG_SPL_BUILD
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