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S5P: Exynos: Add GPIO pin numbering and rename definitions

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This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
  To have consistent 0..n-1 GPIO numbering the banks are divided
  into different parts where ever they have holes in them.

* Rename GPIO definitions from GPIO_... to S5P_GPIO_...
  These changes were done to enable cmd_gpio for EXYNOS and
  cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
  getting a error during compilation.

* Adds support for name to gpio conversion in s5p_gpio to enable
  gpio command EXYNOS SoCs. Function has been added to asm/gpio.h
  to decode the input gpio name to gpio number.
  Example: SMDK5420 # gpio set gpa00

Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
master
Akshay Saraswat 10 years ago committed by Minkyu Kang
parent bfbc47cc9f
commit f6ae1ca058
19 changed files with 2899 additions and 895 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 561
      arch/arm/cpu/armv7/exynos/pinmux.c
  2. 4
      arch/arm/dts/exynos4210-origen.dts
  3. 6
      arch/arm/dts/exynos4210-trats.dts
  4. 4
      arch/arm/dts/exynos4210-universal_c210.dts
  5. 4
      arch/arm/dts/exynos4412-trats2.dts
  6. 17
      arch/arm/include/asm/arch-exynos/cpu.h
  7. 1761
      arch/arm/include/asm/arch-exynos/gpio.h
  8. 948
      arch/arm/include/asm/arch-s5pc1xx/gpio.h
  9. 11
      board/samsung/arndale/arndale.c
  10. 32
      board/samsung/goni/goni.c
  11. 20
      board/samsung/smdk5250/exynos5-dt.c
  12. 19
      board/samsung/smdk5250/smdk5250.c
  13. 15
      board/samsung/smdk5420/smdk5420.c
  14. 5
      board/samsung/smdkc100/smdkc100.c
  15. 19
      board/samsung/smdkv310/smdkv310.c
  16. 39
      board/samsung/trats/trats.c
  17. 74
      board/samsung/trats2/trats2.c
  18. 51
      board/samsung/universal_c210/universal.c
  19. 204
      drivers/gpio/s5p_gpio.c

561
arch/arm/cpu/armv7/exynos/pinmux.c
Unescape View File

@ -13,30 +13,23 @@
static void exynos5_uart_config(int peripheral)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
bank = &gpio1->a0;
start = 0;
start = EXYNOS5_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
bank = &gpio1->d0;
start = 0;
start = EXYNOS5_GPIO_D00;
count = 4;
break;
case PERIPH_ID_UART2:
bank = &gpio1->a1;
start = 0;
start = EXYNOS5_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
bank = &gpio1->a1;
start = 4;
start = EXYNOS5_GPIO_A14;
count = 2;
break;
default:
@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral)
return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static void exynos5420_uart_config(int peripheral)
{
struct exynos5420_gpio_part1 *gpio1 =
(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
bank = &gpio1->a0;
start = 0;
start = EXYNOS5420_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
bank = &gpio1->a0;
start = 4;
start = EXYNOS5420_GPIO_A04;
count = 4;
break;
case PERIPH_ID_UART2:
bank = &gpio1->a1;
start = 0;
start = EXYNOS5420_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
bank = &gpio1->a1;
start = 4;
start = EXYNOS5420_GPIO_A14;
count = 2;
break;
default:
@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral)
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static int exynos5_mmc_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
int i, start = 0, gpio_func = 0;
int i, start, start_ext, gpio_func = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio1->c0;
bank_ext = &gpio1->c1;
start = 0;
gpio_func = GPIO_FUNC(0x2);
start = EXYNOS5_GPIO_C00;
start_ext = EXYNOS5_GPIO_C10;
gpio_func = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SDMMC1:
bank = &gpio1->c2;
bank_ext = NULL;
start = EXYNOS5_GPIO_C20;
start_ext = 0;
break;
case PERIPH_ID_SDMMC2:
bank = &gpio1->c3;
bank_ext = &gpio1->c4;
start = 3;
gpio_func = GPIO_FUNC(0x3);
start = EXYNOS5_GPIO_C30;
start_ext = EXYNOS5_GPIO_C43;
gpio_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC3:
bank = &gpio1->c4;
bank_ext = NULL;
start = EXYNOS5_GPIO_C40;
start_ext = 0;
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start; i <= (start + 3); i++) {
s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
for (i = start_ext; i <= (start_ext + 3); i++) {
gpio_cfg_pin(i, gpio_func);
gpio_set_pull(i, S5P_GPIO_PULL_UP);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
for (i = start; i < (start + 2); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
for (i = (start + 3); i <= (start + 6); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_UP);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
return 0;
@ -148,26 +129,20 @@ static int exynos5_mmc_config(int peripheral, int flags)
static int exynos5420_mmc_config(int peripheral, int flags)
{
struct exynos5420_gpio_part3 *gpio3 =
(struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
int i, start;
int i, start = 0, start_ext = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio3->c0;
bank_ext = &gpio3->c3;
start = 0;
start = EXYNOS5420_GPIO_C00;
start_ext = EXYNOS5420_GPIO_C30;
break;
case PERIPH_ID_SDMMC1:
bank = &gpio3->c1;
bank_ext = &gpio3->d1;
start = 4;
start = EXYNOS5420_GPIO_C10;
start_ext = EXYNOS5420_GPIO_D14;
break;
case PERIPH_ID_SDMMC2:
bank = &gpio3->c2;
bank_ext = NULL;
start = 0;
start = EXYNOS5420_GPIO_C20;
start_ext = 0;
break;
default:
start = 0;
@ -175,41 +150,41 @@ static int exynos5420_mmc_config(int peripheral, int flags)
return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start; i <= (start + 3); i++) {
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
for (i = start_ext; i <= (start_ext + 3); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_UP);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
for (i = 0; i < 3; i++) {
for (i = start; i < (start + 3); i++) {
/*
* MMC0 is intended to be used for eMMC. The
* card detect pin is used as a VDDEN signal to
* power on the eMMC. The 5420 iROM makes
* this same assumption.
*/
if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
s5p_gpio_set_value(bank, i, 1);
s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
gpio_set_value(i, 1);
gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
} else {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
for (i = (start + 3); i <= (start + 6); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_UP);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
return 0;
@ -217,8 +192,6 @@ static int exynos5420_mmc_config(int peripheral, int flags)
static void exynos5_sromc_config(int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
int i;
/*
@ -236,13 +209,13 @@ static void exynos5_sromc_config(int flags)
* GPY1[2] SROM_WAIT(2)
* GPY1[3] EBI_DATA_RDn(2)
*/
s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
for (i = 0; i < 4; i++)
s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
/*
* EBI: 8 Addrss Lines
@ -277,108 +250,101 @@ static void exynos5_sromc_config(int flags)
* GPY6[7] EBI_DATA[15](2)
*/
for (i = 0; i < 8; i++) {
s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
}
}
static void exynos5_i2c_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
switch (peripheral) {
case PERIPH_ID_I2C0:
s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
break;
}
}
static void exynos5420_i2c_config(int peripheral)
{
struct exynos5420_gpio_part1 *gpio1 =
(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
switch (peripheral) {
case PERIPH_ID_I2C0:
s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C8:
s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C9:
s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C10:
s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
break;
}
}
@ -386,19 +352,15 @@ static void exynos5420_i2c_config(int peripheral)
static void exynos5_i2s_config(int peripheral)
{
int i;
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos5_gpio_part4 *gpio4 =
(struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
switch (peripheral) {
case PERIPH_ID_I2S0:
for (i = 0; i < 5; i++)
s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
break;
case PERIPH_ID_I2S1:
for (i = 0; i < 5; i++)
s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
break;
}
}
@ -406,75 +368,57 @@ static void exynos5_i2s_config(int peripheral)
void exynos5_spi_config(int peripheral)
{
int cfg = 0, pin = 0, i;
struct s5p_gpio_bank *bank = NULL;
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct exynos5_gpio_part2 *gpio2 =
(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
switch (peripheral) {
case PERIPH_ID_SPI0:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 0;
cfg = S5P_GPIO_FUNC(0x2);
pin = EXYNOS5_GPIO_A20;
break;
case PERIPH_ID_SPI1:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 4;
cfg = S5P_GPIO_FUNC(0x2);
pin = EXYNOS5_GPIO_A24;
break;
case PERIPH_ID_SPI2:
bank = &gpio1->b1;
cfg = GPIO_FUNC(0x5);
pin = 1;
cfg = S5P_GPIO_FUNC(0x5);
pin = EXYNOS5_GPIO_B11;
break;
case PERIPH_ID_SPI3:
bank = &gpio2->f1;
cfg = GPIO_FUNC(0x2);
pin = 0;
cfg = S5P_GPIO_FUNC(0x2);
pin = EXYNOS5_GPIO_F10;
break;
case PERIPH_ID_SPI4:
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
}
break;
}
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
s5p_gpio_cfg_pin(bank, i, cfg);
gpio_cfg_pin(i, cfg);
}
}
void exynos5420_spi_config(int peripheral)
{
int cfg, pin, i;
struct s5p_gpio_bank *bank = NULL;
struct exynos5420_gpio_part1 *gpio1 =
(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos5420_gpio_part4 *gpio4 =
(struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
switch (peripheral) {
case PERIPH_ID_SPI0:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 0;
pin = EXYNOS5420_GPIO_A20;
cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI1:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 4;
pin = EXYNOS5420_GPIO_A24;
cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI2:
bank = &gpio1->b1;
cfg = GPIO_FUNC(0x5);
pin = 1;
pin = EXYNOS5420_GPIO_B11;
cfg = S5P_GPIO_FUNC(0x5);
break;
case PERIPH_ID_SPI3:
bank = &gpio4->f1;
cfg = GPIO_FUNC(0x2);
pin = 0;
pin = EXYNOS5420_GPIO_F10;
cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI4:
cfg = 0;
@ -489,11 +433,13 @@ void exynos5420_spi_config(int peripheral)
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
s5p_gpio_cfg_pin(bank, i, cfg);
gpio_cfg_pin(i, cfg);
} else {
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
S5P_GPIO_FUNC(0x4));
}
}
}
@ -588,76 +534,70 @@ static int exynos5420_pinmux_config(int peripheral, int flags)
static void exynos4_i2c_config(int peripheral, int flags)
{
struct exynos4_gpio_part1 *gpio1 =
(struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
switch (peripheral) {
case PERIPH_ID_I2C0:
s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
break;
}
}
static int exynos4_mmc_config(int peripheral, int flags)
{
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
struct s5p_gpio_bank *bank, *bank_ext;
int i;
int i, start = 0, start_ext = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio2->k0;
bank_ext = &gpio2->k1;
start = EXYNOS4_GPIO_K00;
start_ext = EXYNOS4_GPIO_K13;
break;
case PERIPH_ID_SDMMC2:
bank = &gpio2->k2;
bank_ext = &gpio2->k3;
start = EXYNOS4_GPIO_K20;
start_ext = EXYNOS4_GPIO_K33;
break;
default:
return -1;
}
for (i = 0; i < 7; i++) {
if (i == 2)
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = 3; i < 7; i++) {
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
for (i = start_ext; i < (start_ext + 4); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
@ -666,41 +606,138 @@ static int exynos4_mmc_config(int peripheral, int flags)
static void exynos4_uart_config(int peripheral)
{
struct exynos4_gpio_part1 *gpio1 =
(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
bank = &gpio1->a0;
start = 0;
start = EXYNOS4_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
bank = &gpio1->a0;
start = 4;
start = EXYNOS4_GPIO_A04;
count = 4;
break;
case PERIPH_ID_UART2:
bank = &gpio1->a1;
start = 0;
start = EXYNOS4_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
bank = &gpio1->a1;
start = 4;
start = EXYNOS4_GPIO_A14;
count = 2;
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
for (i = start; i < (start + count); i++) {
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static void exynos4x12_i2c_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_I2C0:
gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
break;
}
}
static int exynos4x12_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4X12_GPIO_K00;
start_ext = EXYNOS4X12_GPIO_K13;
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4X12_GPIO_K20;
start_ext = EXYNOS4X12_GPIO_K33;
break;
default:
return -1;
}
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
return 0;
}
static void exynos4x12_uart_config(int peripheral)
{
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
start = EXYNOS4X12_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
start = EXYNOS4X12_GPIO_A04;
count = 4;
break;
case PERIPH_ID_UART2:
start = EXYNOS4X12_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
start = EXYNOS4X12_GPIO_A14;
count = 2;
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return;
}
for (i = start; i < (start + count); i++) {
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static int exynos4_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@ -736,6 +773,41 @@ static int exynos4_pinmux_config(int peripheral, int flags)
return 0;
}
static int exynos4x12_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_UART0:
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
exynos4x12_uart_config(peripheral);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
exynos4x12_i2c_config(peripheral, flags);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
return exynos4x12_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
return 0;
}
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5()) {
@ -744,11 +816,14 @@ int exynos_pinmux_config(int peripheral, int flags)
else if (proid_is_exynos5250())
return exynos5_pinmux_config(peripheral, flags);
} else if (cpu_is_exynos4()) {
return exynos4_pinmux_config(peripheral, flags);
} else {
debug("pinmux functionality not supported\n");
if (proid_is_exynos4412())
return exynos4x12_pinmux_config(peripheral, flags);
else
return exynos4_pinmux_config(peripheral, flags);
}
debug("pinmux functionality not supported\n");
return -1;
}
@ -787,7 +862,7 @@ int pinmux_decode_periph_id(const void *blob, int node)
return exynos5_pinmux_decode_periph_id(blob, node);
else if (cpu_is_exynos4())
return exynos4_pinmux_decode_periph_id(blob, node);
else
return PERIPH_ID_NONE;
return PERIPH_ID_NONE;
}
#endif

4
arch/arm/dts/exynos4210-origen.dts
Unescape View File

@ -36,10 +36,10 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x2008002 0>;
cd-gpios = <&gpio 0xA2 0>;
};
sdhci@12540000 {
status = "disabled";
};
};
};

6
arch/arm/dts/exynos4210-trats.dts
Unescape View File

@ -101,7 +101,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0x2008002 0>;
pwr-gpios = <&gpio 0xA2 0>;
};
sdhci@12520000 {
@ -111,10 +111,10 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x20c6004 0>;
cd-gpios = <&gpio 0x39C 0>;
};
sdhci@12540000 {
status = "disabled";
};
};
};

4
arch/arm/dts/exynos4210-universal_c210.dts
Unescape View File

@ -24,7 +24,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0x2008002 0>;
pwr-gpios = <&gpio 0xA2 0>;
};
sdhci@12520000 {
@ -34,7 +34,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x20c6004 0>;
cd-gpios = <&gpio 0x39C 0>;
};
sdhci@12540000 {

4
arch/arm/dts/exynos4412-trats2.dts
Unescape View File

@ -415,7 +415,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0x2004002 0>;
pwr-gpios = <&gpio 0xB2 0>;
};
sdhci@12520000 {
@ -425,7 +425,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x20C6004 0>;
cd-gpios = <&gpio 0x3BC 0>;
};
sdhci@12540000 {

17
arch/arm/include/asm/arch-exynos/cpu.h
Unescape View File

@ -98,7 +98,7 @@
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_AUDIOSS_BASE 0x03810000
#define EXYNOS5_GPIO_PART4_BASE 0x03860000
#define EXYNOS5_GPIO_PART8_BASE 0x03860000
#define EXYNOS5_PRO_ID 0x10000000
#define EXYNOS5_CLOCK_BASE 0x10010000
#define EXYNOS5_POWER_BASE 0x10040000
@ -108,9 +108,13 @@
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY_BASE 0x10C00000
#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
#define EXYNOS5_GPIO_PART5_BASE 0x10D10000
#define EXYNOS5_GPIO_PART6_BASE 0x10D10060
#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
#define EXYNOS5_GPIO_PART2_BASE 0x114002E0
#define EXYNOS5_GPIO_PART3_BASE 0x11400C00
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
#define EXYNOS5_USB3PHY_BASE 0x12100000
@ -125,7 +129,7 @@
#define EXYNOS5_I2S_BASE 0x12D60000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_SPI_ISP_BASE 0x131A0000
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
#define EXYNOS5_GPIO_PART4_BASE 0x13400000
#define EXYNOS5_FIMD_BASE 0x14400000
#define EXYNOS5_DP_BASE 0x145B0000
@ -135,7 +139,7 @@
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE 0x03810000
#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
#define EXYNOS5420_GPIO_PART6_BASE 0x03860000
#define EXYNOS5420_PRO_ID 0x10000000
#define EXYNOS5420_CLOCK_BASE 0x10010000
#define EXYNOS5420_POWER_BASE 0x10040000
@ -158,8 +162,9 @@
#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
#define EXYNOS5420_GPIO_PART3_BASE 0x13410000
#define EXYNOS5420_GPIO_PART4_BASE 0x14000000
#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
#define EXYNOS5420_GPIO_PART4_BASE 0x13410000
#define EXYNOS5420_GPIO_PART5_BASE 0x14000000
#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
#define EXYNOS5420_DP_BASE 0x145B0000

1761
arch/arm/include/asm/arch-exynos/gpio.h
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File diff suppressed because it is too large Load Diff

948
arch/arm/include/asm/arch-s5pc1xx/gpio.h
Unescape View File

@ -19,170 +19,830 @@ struct s5p_gpio_bank {
unsigned char res1[8];
};
struct s5pc100_gpio {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
struct s5p_gpio_bank b;
struct s5p_gpio_bank c;
struct s5p_gpio_bank d;
struct s5p_gpio_bank e0;
struct s5p_gpio_bank e1;
struct s5p_gpio_bank f0;
struct s5p_gpio_bank f1;
struct s5p_gpio_bank f2;
struct s5p_gpio_bank f3;
struct s5p_gpio_bank g0;
struct s5p_gpio_bank g1;
struct s5p_gpio_bank g2;
struct s5p_gpio_bank g3;
struct s5p_gpio_bank i;
struct s5p_gpio_bank j0;
struct s5p_gpio_bank j1;
struct s5p_gpio_bank j2;
struct s5p_gpio_bank j3;
struct s5p_gpio_bank j4;
struct s5p_gpio_bank k0;
struct s5p_gpio_bank k1;
struct s5p_gpio_bank k2;
struct s5p_gpio_bank k3;
struct s5p_gpio_bank l0;
struct s5p_gpio_bank l1;
struct s5p_gpio_bank l2;
struct s5p_gpio_bank l3;
struct s5p_gpio_bank l4;
struct s5p_gpio_bank h0;
struct s5p_gpio_bank h1;
struct s5p_gpio_bank h2;
struct s5p_gpio_bank h3;
/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
enum s5pc100_gpio_pin {
S5PC100_GPIO_A00,
S5PC100_GPIO_A01,
S5PC100_GPIO_A02,
S5PC100_GPIO_A03,
S5PC100_GPIO_A04,
S5PC100_GPIO_A05,
S5PC100_GPIO_A06,
S5PC100_GPIO_A07,
S5PC100_GPIO_A10,
S5PC100_GPIO_A11,
S5PC100_GPIO_A12,
S5PC100_GPIO_A13,
S5PC100_GPIO_A14,
S5PC100_GPIO_A15,
S5PC100_GPIO_A16,
S5PC100_GPIO_A17,
S5PC100_GPIO_B0,
S5PC100_GPIO_B1,
S5PC100_GPIO_B2,
S5PC100_GPIO_B3,
S5PC100_GPIO_B4,
S5PC100_GPIO_B5,
S5PC100_GPIO_B6,
S5PC100_GPIO_B7,
S5PC100_GPIO_C0,
S5PC100_GPIO_C1,
S5PC100_GPIO_C2,
S5PC100_GPIO_C3,
S5PC100_GPIO_C4,
S5PC100_GPIO_C5,
S5PC100_GPIO_C6,
S5PC100_GPIO_C7,
S5PC100_GPIO_D0,
S5PC100_GPIO_D1,
S5PC100_GPIO_D2,
S5PC100_GPIO_D3,
S5PC100_GPIO_D4,
S5PC100_GPIO_D5,
S5PC100_GPIO_D6,
S5PC100_GPIO_D7,
S5PC100_GPIO_E00,
S5PC100_GPIO_E01,
S5PC100_GPIO_E02,
S5PC100_GPIO_E03,
S5PC100_GPIO_E04,
S5PC100_GPIO_E05,
S5PC100_GPIO_E06,
S5PC100_GPIO_E07,
S5PC100_GPIO_E10,
S5PC100_GPIO_E11,
S5PC100_GPIO_E12,
S5PC100_GPIO_E13,
S5PC100_GPIO_E14,
S5PC100_GPIO_E15,
S5PC100_GPIO_E16,
S5PC100_GPIO_E17,
S5PC100_GPIO_F00,
S5PC100_GPIO_F01,
S5PC100_GPIO_F02,
S5PC100_GPIO_F03,
S5PC100_GPIO_F04,
S5PC100_GPIO_F05,
S5PC100_GPIO_F06,
S5PC100_GPIO_F07,
S5PC100_GPIO_F10,
S5PC100_GPIO_F11,
S5PC100_GPIO_F12,
S5PC100_GPIO_F13,
S5PC100_GPIO_F14,
S5PC100_GPIO_F15,
S5PC100_GPIO_F16,
S5PC100_GPIO_F17,
S5PC100_GPIO_F20,
S5PC100_GPIO_F21,
S5PC100_GPIO_F22,
S5PC100_GPIO_F23,
S5PC100_GPIO_F24,
S5PC100_GPIO_F25,
S5PC100_GPIO_F26,
S5PC100_GPIO_F27,
S5PC100_GPIO_F30,
S5PC100_GPIO_F31,
S5PC100_GPIO_F32,
S5PC100_GPIO_F33,
S5PC100_GPIO_F34,
S5PC100_GPIO_F35,
S5PC100_GPIO_F36,
S5PC100_GPIO_F37,
S5PC100_GPIO_G00,
S5PC100_GPIO_G01,
S5PC100_GPIO_G02,
S5PC100_GPIO_G03,
S5PC100_GPIO_G04,
S5PC100_GPIO_G05,
S5PC100_GPIO_G06,
S5PC100_GPIO_G07,
S5PC100_GPIO_G10,
S5PC100_GPIO_G11,
S5PC100_GPIO_G12,
S5PC100_GPIO_G13,
S5PC100_GPIO_G14,
S5PC100_GPIO_G15,
S5PC100_GPIO_G16,
S5PC100_GPIO_G17,
S5PC100_GPIO_G20,
S5PC100_GPIO_G21,
S5PC100_GPIO_G22,
S5PC100_GPIO_G23,
S5PC100_GPIO_G24,
S5PC100_GPIO_G25,
S5PC100_GPIO_G26,
S5PC100_GPIO_G27,
S5PC100_GPIO_G30,
S5PC100_GPIO_G31,
S5PC100_GPIO_G32,
S5PC100_GPIO_G33,
S5PC100_GPIO_G34,
S5PC100_GPIO_G35,
S5PC100_GPIO_G36,
S5PC100_GPIO_G37,
S5PC100_GPIO_I0,
S5PC100_GPIO_I1,
S5PC100_GPIO_I2,
S5PC100_GPIO_I3,
S5PC100_GPIO_I4,
S5PC100_GPIO_I5,
S5PC100_GPIO_I6,
S5PC100_GPIO_I7,
S5PC100_GPIO_J00,
S5PC100_GPIO_J01,
S5PC100_GPIO_J02,
S5PC100_GPIO_J03,
S5PC100_GPIO_J04,
S5PC100_GPIO_J05,
S5PC100_GPIO_J06,
S5PC100_GPIO_J07,
S5PC100_GPIO_J10,
S5PC100_GPIO_J11,
S5PC100_GPIO_J12,
S5PC100_GPIO_J13,
S5PC100_GPIO_J14,
S5PC100_GPIO_J15,
S5PC100_GPIO_J16,
S5PC100_GPIO_J17,
S5PC100_GPIO_J20,
S5PC100_GPIO_J21,
S5PC100_GPIO_J22,
S5PC100_GPIO_J23,
S5PC100_GPIO_J24,
S5PC100_GPIO_J25,
S5PC100_GPIO_J26,
S5PC100_GPIO_J27,
S5PC100_GPIO_J30,
S5PC100_GPIO_J31,
S5PC100_GPIO_J32,
S5PC100_GPIO_J33,
S5PC100_GPIO_J34,
S5PC100_GPIO_J35,
S5PC100_GPIO_J36,
S5PC100_GPIO_J37,
S5PC100_GPIO_J40,
S5PC100_GPIO_J41,
S5PC100_GPIO_J42,
S5PC100_GPIO_J43,
S5PC100_GPIO_J44,
S5PC100_GPIO_J45,
S5PC100_GPIO_J46,
S5PC100_GPIO_J47,
S5PC100_GPIO_K00,
S5PC100_GPIO_K01,
S5PC100_GPIO_K02,
S5PC100_GPIO_K03,
S5PC100_GPIO_K04,
S5PC100_GPIO_K05,
S5PC100_GPIO_K06,
S5PC100_GPIO_K07,
S5PC100_GPIO_K10,
S5PC100_GPIO_K11,
S5PC100_GPIO_K12,
S5PC100_GPIO_K13,
S5PC100_GPIO_K14,
S5PC100_GPIO_K15,
S5PC100_GPIO_K16,
S5PC100_GPIO_K17,
S5PC100_GPIO_K20,
S5PC100_GPIO_K21,
S5PC100_GPIO_K22,
S5PC100_GPIO_K23,
S5PC100_GPIO_K24,
S5PC100_GPIO_K25,
S5PC100_GPIO_K26,
S5PC100_GPIO_K27,
S5PC100_GPIO_K30,
S5PC100_GPIO_K31,
S5PC100_GPIO_K32,
S5PC100_GPIO_K33,
S5PC100_GPIO_K34,
S5PC100_GPIO_K35,
S5PC100_GPIO_K36,
S5PC100_GPIO_K37,
S5PC100_GPIO_L00,
S5PC100_GPIO_L01,
S5PC100_GPIO_L02,
S5PC100_GPIO_L03,
S5PC100_GPIO_L04,
S5PC100_GPIO_L05,
S5PC100_GPIO_L06,
S5PC100_GPIO_L07,
S5PC100_GPIO_L10,
S5PC100_GPIO_L11,
S5PC100_GPIO_L12,
S5PC100_GPIO_L13,
S5PC100_GPIO_L14,
S5PC100_GPIO_L15,
S5PC100_GPIO_L16,
S5PC100_GPIO_L17,
S5PC100_GPIO_L20,
S5PC100_GPIO_L21,
S5PC100_GPIO_L22,
S5PC100_GPIO_L23,
S5PC100_GPIO_L24,
S5PC100_GPIO_L25,
S5PC100_GPIO_L26,
S5PC100_GPIO_L27,
S5PC100_GPIO_L30,
S5PC100_GPIO_L31,
S5PC100_GPIO_L32,
S5PC100_GPIO_L33,
S5PC100_GPIO_L34,
S5PC100_GPIO_L35,
S5PC100_GPIO_L36,
S5PC100_GPIO_L37,
S5PC100_GPIO_L40,
S5PC100_GPIO_L41,
S5PC100_GPIO_L42,
S5PC100_GPIO_L43,
S5PC100_GPIO_L44,
S5PC100_GPIO_L45,
S5PC100_GPIO_L46,
S5PC100_GPIO_L47,
S5PC100_GPIO_H00,
S5PC100_GPIO_H01,
S5PC100_GPIO_H02,
S5PC100_GPIO_H03,
S5PC100_GPIO_H04,
S5PC100_GPIO_H05,
S5PC100_GPIO_H06,
S5PC100_GPIO_H07,
S5PC100_GPIO_H10,
S5PC100_GPIO_H11,
S5PC100_GPIO_H12,
S5PC100_GPIO_H13,
S5PC100_GPIO_H14,
S5PC100_GPIO_H15,
S5PC100_GPIO_H16,
S5PC100_GPIO_H17,
S5PC100_GPIO_H20,
S5PC100_GPIO_H21,
S5PC100_GPIO_H22,
S5PC100_GPIO_H23,
S5PC100_GPIO_H24,
S5PC100_GPIO_H25,
S5PC100_GPIO_H26,
S5PC100_GPIO_H27,
S5PC100_GPIO_H30,
S5PC100_GPIO_H31,
S5PC100_GPIO_H32,
S5PC100_GPIO_H33,
S5PC100_GPIO_H34,
S5PC100_GPIO_H35,
S5PC100_GPIO_H36,
S5PC100_GPIO_H37,
S5PC100_GPIO_MAX_PORT
};
struct s5pc110_gpio {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
struct s5p_gpio_bank b;
struct s5p_gpio_bank c0;
struct s5p_gpio_bank c1;
struct s5p_gpio_bank d0;
struct s5p_gpio_bank d1;
struct s5p_gpio_bank e0;
struct s5p_gpio_bank e1;
struct s5p_gpio_bank f0;
struct s5p_gpio_bank f1;
struct s5p_gpio_bank f2;
struct s5p_gpio_bank f3;
struct s5p_gpio_bank g0;
struct s5p_gpio_bank g1;
struct s5p_gpio_bank g2;
struct s5p_gpio_bank g3;
struct s5p_gpio_bank i;
struct s5p_gpio_bank j0;
struct s5p_gpio_bank j1;
struct s5p_gpio_bank j2;
struct s5p_gpio_bank j3;
struct s5p_gpio_bank j4;
struct s5p_gpio_bank mp0_1;
struct s5p_gpio_bank mp0_2;
struct s5p_gpio_bank mp0_3;
struct s5p_gpio_bank mp0_4;
struct s5p_gpio_bank mp0_5;
struct s5p_gpio_bank mp0_6;
struct s5p_gpio_bank mp0_7;
struct s5p_gpio_bank mp1_0;
struct s5p_gpio_bank mp1_1;
struct s5p_gpio_bank mp1_2;
struct s5p_gpio_bank mp1_3;
struct s5p_gpio_bank mp1_4;
struct s5p_gpio_bank mp1_5;
struct s5p_gpio_bank mp1_6;
struct s5p_gpio_bank mp1_7;
struct s5p_gpio_bank mp1_8;
struct s5p_gpio_bank mp2_0;
struct s5p_gpio_bank mp2_1;
struct s5p_gpio_bank mp2_2;
struct s5p_gpio_bank mp2_3;
struct s5p_gpio_bank mp2_4;
struct s5p_gpio_bank mp2_5;
struct s5p_gpio_bank mp2_6;
struct s5p_gpio_bank mp2_7;
struct s5p_gpio_bank mp2_8;
struct s5p_gpio_bank res1[48];
struct s5p_gpio_bank h0;
struct s5p_gpio_bank h1;
struct s5p_gpio_bank h2;
struct s5p_gpio_bank h3;
enum s5pc110_gpio_pin {
S5PC110_GPIO_A00,
S5PC110_GPIO_A01,
S5PC110_GPIO_A02,
S5PC110_GPIO_A03,
S5PC110_GPIO_A04,
S5PC110_GPIO_A05,
S5PC110_GPIO_A06,
S5PC110_GPIO_A07,
S5PC110_GPIO_A10,
S5PC110_GPIO_A11,
S5PC110_GPIO_A12,
S5PC110_GPIO_A13,
S5PC110_GPIO_A14,
S5PC110_GPIO_A15,
S5PC110_GPIO_A16,
S5PC110_GPIO_A17,
S5PC110_GPIO_B0,
S5PC110_GPIO_B1,
S5PC110_GPIO_B2,
S5PC110_GPIO_B3,
S5PC110_GPIO_B4,
S5PC110_GPIO_B5,
S5PC110_GPIO_B6,
S5PC110_GPIO_B7,
S5PC110_GPIO_C00,
S5PC110_GPIO_C01,
S5PC110_GPIO_C02,
S5PC110_GPIO_C03,
S5PC110_GPIO_C04,
S5PC110_GPIO_C05,
S5PC110_GPIO_C06,
S5PC110_GPIO_C07,
S5PC110_GPIO_C10,
S5PC110_GPIO_C11,
S5PC110_GPIO_C12,
S5PC110_GPIO_C13,
S5PC110_GPIO_C14,
S5PC110_GPIO_C15,
S5PC110_GPIO_C16,
S5PC110_GPIO_C17,
S5PC110_GPIO_D00,
S5PC110_GPIO_D01,
S5PC110_GPIO_D02,
S5PC110_GPIO_D03,
S5PC110_GPIO_D04,
S5PC110_GPIO_D05,
S5PC110_GPIO_D06,
S5PC110_GPIO_D07,
S5PC110_GPIO_D10,
S5PC110_GPIO_D11,
S5PC110_GPIO_D12,
S5PC110_GPIO_D13,
S5PC110_GPIO_D14,
S5PC110_GPIO_D15,
S5PC110_GPIO_D16,
S5PC110_GPIO_D17,
S5PC110_GPIO_E00,
S5PC110_GPIO_E01,
S5PC110_GPIO_E02,
S5PC110_GPIO_E03,
S5PC110_GPIO_E04,
S5PC110_GPIO_E05,
S5PC110_GPIO_E06,
S5PC110_GPIO_E07,
S5PC110_GPIO_E10,
S5PC110_GPIO_E11,
S5PC110_GPIO_E12,
S5PC110_GPIO_E13,
S5PC110_GPIO_E14,
S5PC110_GPIO_E15,
S5PC110_GPIO_E16,
S5PC110_GPIO_E17,
S5PC110_GPIO_F00,
S5PC110_GPIO_F01,
S5PC110_GPIO_F02,
S5PC110_GPIO_F03,
S5PC110_GPIO_F04,
S5PC110_GPIO_F05,
S5PC110_GPIO_F06,
S5PC110_GPIO_F07,
S5PC110_GPIO_F10,
S5PC110_GPIO_F11,
S5PC110_GPIO_F12,
S5PC110_GPIO_F13,
S5PC110_GPIO_F14,
S5PC110_GPIO_F15,
S5PC110_GPIO_F16,
S5PC110_GPIO_F17,
S5PC110_GPIO_F20,
S5PC110_GPIO_F21,
S5PC110_GPIO_F22,
S5PC110_GPIO_F23,
S5PC110_GPIO_F24,
S5PC110_GPIO_F25,
S5PC110_GPIO_F26,
S5PC110_GPIO_F27,
S5PC110_GPIO_F30,
S5PC110_GPIO_F31,
S5PC110_GPIO_F32,
S5PC110_GPIO_F33,
S5PC110_GPIO_F34,
S5PC110_GPIO_F35,
S5PC110_GPIO_F36,
S5PC110_GPIO_F37,
S5PC110_GPIO_G00,
S5PC110_GPIO_G01,
S5PC110_GPIO_G02,
S5PC110_GPIO_G03,
S5PC110_GPIO_G04,
S5PC110_GPIO_G05,
S5PC110_GPIO_G06,
S5PC110_GPIO_G07,
S5PC110_GPIO_G10,
S5PC110_GPIO_G11,
S5PC110_GPIO_G12,
S5PC110_GPIO_G13,
S5PC110_GPIO_G14,
S5PC110_GPIO_G15,
S5PC110_GPIO_G16,
S5PC110_GPIO_G17,
S5PC110_GPIO_G20,
S5PC110_GPIO_G21,
S5PC110_GPIO_G22,
S5PC110_GPIO_G23,
S5PC110_GPIO_G24,
S5PC110_GPIO_G25,
S5PC110_GPIO_G26,
S5PC110_GPIO_G27,
S5PC110_GPIO_G30,
S5PC110_GPIO_G31,
S5PC110_GPIO_G32,
S5PC110_GPIO_G33,
S5PC110_GPIO_G34,
S5PC110_GPIO_G35,
S5PC110_GPIO_G36,
S5PC110_GPIO_G37,
S5PC110_GPIO_I0,
S5PC110_GPIO_I1,
S5PC110_GPIO_I2,
S5PC110_GPIO_I3,
S5PC110_GPIO_I4,
S5PC110_GPIO_I5,
S5PC110_GPIO_I6,
S5PC110_GPIO_I7,
S5PC110_GPIO_J00,
S5PC110_GPIO_J01,
S5PC110_GPIO_J02,
S5PC110_GPIO_J03,
S5PC110_GPIO_J04,
S5PC110_GPIO_J05,
S5PC110_GPIO_J06,
S5PC110_GPIO_J07,
S5PC110_GPIO_J10,
S5PC110_GPIO_J11,
S5PC110_GPIO_J12,
S5PC110_GPIO_J13,
S5PC110_GPIO_J14,
S5PC110_GPIO_J15,
S5PC110_GPIO_J16,
S5PC110_GPIO_J17,
S5PC110_GPIO_J20,
S5PC110_GPIO_J21,
S5PC110_GPIO_J22,
S5PC110_GPIO_J23,
S5PC110_GPIO_J24,
S5PC110_GPIO_J25,
S5PC110_GPIO_J26,
S5PC110_GPIO_J27,
S5PC110_GPIO_J30,
S5PC110_GPIO_J31,
S5PC110_GPIO_J32,
S5PC110_GPIO_J33,
S5PC110_GPIO_J34,
S5PC110_GPIO_J35,
S5PC110_GPIO_J36,
S5PC110_GPIO_J37,
S5PC110_GPIO_J40,
S5PC110_GPIO_J41,
S5PC110_GPIO_J42,
S5PC110_GPIO_J43,
S5PC110_GPIO_J44,
S5PC110_GPIO_J45,
S5PC110_GPIO_J46,
S5PC110_GPIO_J47,
S5PC110_GPIO_MP010,
S5PC110_GPIO_MP011,
S5PC110_GPIO_MP012,
S5PC110_GPIO_MP013,
S5PC110_GPIO_MP014,
S5PC110_GPIO_MP015,
S5PC110_GPIO_MP016,
S5PC110_GPIO_MP017,
S5PC110_GPIO_MP020,
S5PC110_GPIO_MP021,
S5PC110_GPIO_MP022,
S5PC110_GPIO_MP023,
S5PC110_GPIO_MP024,
S5PC110_GPIO_MP025,
S5PC110_GPIO_MP026,
S5PC110_GPIO_MP027,
S5PC110_GPIO_MP030,
S5PC110_GPIO_MP031,
S5PC110_GPIO_MP032,
S5PC110_GPIO_MP033,
S5PC110_GPIO_MP034,
S5PC110_GPIO_MP035,
S5PC110_GPIO_MP036,
S5PC110_GPIO_MP037,
S5PC110_GPIO_MP040,
S5PC110_GPIO_MP041,
S5PC110_GPIO_MP042,
S5PC110_GPIO_MP043,
S5PC110_GPIO_MP044,
S5PC110_GPIO_MP045,
S5PC110_GPIO_MP046,
S5PC110_GPIO_MP047,
S5PC110_GPIO_MP050,
S5PC110_GPIO_MP051,
S5PC110_GPIO_MP052,
S5PC110_GPIO_MP053,
S5PC110_GPIO_MP054,
S5PC110_GPIO_MP055,
S5PC110_GPIO_MP056,
S5PC110_GPIO_MP057,
S5PC110_GPIO_MP060,
S5PC110_GPIO_MP061,
S5PC110_GPIO_MP062,
S5PC110_GPIO_MP063,
S5PC110_GPIO_MP064,
S5PC110_GPIO_MP065,
S5PC110_GPIO_MP066,
S5PC110_GPIO_MP067,
S5PC110_GPIO_MP070,
S5PC110_GPIO_MP071,
S5PC110_GPIO_MP072,
S5PC110_GPIO_MP073,
S5PC110_GPIO_MP074,
S5PC110_GPIO_MP075,
S5PC110_GPIO_MP076,
S5PC110_GPIO_MP077,
S5PC110_GPIO_MP100,
S5PC110_GPIO_MP101,
S5PC110_GPIO_MP102,
S5PC110_GPIO_MP103,
S5PC110_GPIO_MP104,
S5PC110_GPIO_MP105,
S5PC110_GPIO_MP106,
S5PC110_GPIO_MP107,
S5PC110_GPIO_MP110,
S5PC110_GPIO_MP111,
S5PC110_GPIO_MP112,
S5PC110_GPIO_MP113,
S5PC110_GPIO_MP114,
S5PC110_GPIO_MP115,
S5PC110_GPIO_MP116,
S5PC110_GPIO_MP117,
S5PC110_GPIO_MP120,
S5PC110_GPIO_MP121,
S5PC110_GPIO_MP122,
S5PC110_GPIO_MP123,
S5PC110_GPIO_MP124,
S5PC110_GPIO_MP125,
S5PC110_GPIO_MP126,
S5PC110_GPIO_MP127,
S5PC110_GPIO_MP130,
S5PC110_GPIO_MP131,
S5PC110_GPIO_MP132,
S5PC110_GPIO_MP133,
S5PC110_GPIO_MP134,
S5PC110_GPIO_MP135,
S5PC110_GPIO_MP136,
S5PC110_GPIO_MP137,
S5PC110_GPIO_MP140,
S5PC110_GPIO_MP141,
S5PC110_GPIO_MP142,
S5PC110_GPIO_MP143,
S5PC110_GPIO_MP144,
S5PC110_GPIO_MP145,
S5PC110_GPIO_MP146,
S5PC110_GPIO_MP147,
S5PC110_GPIO_MP150,
S5PC110_GPIO_MP151,
S5PC110_GPIO_MP152,
S5PC110_GPIO_MP153,
S5PC110_GPIO_MP154,
S5PC110_GPIO_MP155,
S5PC110_GPIO_MP156,
S5PC110_GPIO_MP157,
S5PC110_GPIO_MP160,
S5PC110_GPIO_MP161,
S5PC110_GPIO_MP162,
S5PC110_GPIO_MP163,
S5PC110_GPIO_MP164,
S5PC110_GPIO_MP165,
S5PC110_GPIO_MP166,
S5PC110_GPIO_MP167,
S5PC110_GPIO_MP170,
S5PC110_GPIO_MP171,
S5PC110_GPIO_MP172,
S5PC110_GPIO_MP173,
S5PC110_GPIO_MP174,
S5PC110_GPIO_MP175,
S5PC110_GPIO_MP176,
S5PC110_GPIO_MP177,
S5PC110_GPIO_MP180,
S5PC110_GPIO_MP181,
S5PC110_GPIO_MP182,
S5PC110_GPIO_MP183,
S5PC110_GPIO_MP184,
S5PC110_GPIO_MP185,
S5PC110_GPIO_MP186,
S5PC110_GPIO_MP187,
S5PC110_GPIO_MP200,
S5PC110_GPIO_MP201,
S5PC110_GPIO_MP202,
S5PC110_GPIO_MP203,
S5PC110_GPIO_MP204,
S5PC110_GPIO_MP205,
S5PC110_GPIO_MP206,
S5PC110_GPIO_MP207,
S5PC110_GPIO_MP210,
S5PC110_GPIO_MP211,
S5PC110_GPIO_MP212,
S5PC110_GPIO_MP213,
S5PC110_GPIO_MP214,
S5PC110_GPIO_MP215,
S5PC110_GPIO_MP216,
S5PC110_GPIO_MP217,
S5PC110_GPIO_MP220,
S5PC110_GPIO_MP221,
S5PC110_GPIO_MP222,
S5PC110_GPIO_MP223,
S5PC110_GPIO_MP224,
S5PC110_GPIO_MP225,
S5PC110_GPIO_MP226,
S5PC110_GPIO_MP227,
S5PC110_GPIO_MP230,
S5PC110_GPIO_MP231,
S5PC110_GPIO_MP232,
S5PC110_GPIO_MP233,
S5PC110_GPIO_MP234,
S5PC110_GPIO_MP235,
S5PC110_GPIO_MP236,
S5PC110_GPIO_MP237,
S5PC110_GPIO_MP240,
S5PC110_GPIO_MP241,
S5PC110_GPIO_MP242,
S5PC110_GPIO_MP243,
S5PC110_GPIO_MP244,
S5PC110_GPIO_MP245,
S5PC110_GPIO_MP246,
S5PC110_GPIO_MP247,
S5PC110_GPIO_MP250,
S5PC110_GPIO_MP251,
S5PC110_GPIO_MP252,
S5PC110_GPIO_MP253,
S5PC110_GPIO_MP254,
S5PC110_GPIO_MP255,
S5PC110_GPIO_MP256,
S5PC110_GPIO_MP257,
S5PC110_GPIO_MP260,
S5PC110_GPIO_MP261,
S5PC110_GPIO_MP262,
S5PC110_GPIO_MP263,
S5PC110_GPIO_MP264,
S5PC110_GPIO_MP265,
S5PC110_GPIO_MP266,
S5PC110_GPIO_MP267,
S5PC110_GPIO_MP270,
S5PC110_GPIO_MP271,
S5PC110_GPIO_MP272,
S5PC110_GPIO_MP273,
S5PC110_GPIO_MP274,
S5PC110_GPIO_MP275,
S5PC110_GPIO_MP276,
S5PC110_GPIO_MP277,
S5PC110_GPIO_MP280,
S5PC110_GPIO_MP281,
S5PC110_GPIO_MP282,
S5PC110_GPIO_MP283,
S5PC110_GPIO_MP284,
S5PC110_GPIO_MP285,
S5PC110_GPIO_MP286,
S5PC110_GPIO_MP287,
S5PC110_GPIO_RES,
S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)),
S5PC110_GPIO_H01,
S5PC110_GPIO_H02,
S5PC110_GPIO_H03,
S5PC110_GPIO_H04,
S5PC110_GPIO_H05,
S5PC110_GPIO_H06,
S5PC110_GPIO_H07,
S5PC110_GPIO_H10,
S5PC110_GPIO_H11,
S5PC110_GPIO_H12,
S5PC110_GPIO_H13,
S5PC110_GPIO_H14,
S5PC110_GPIO_H15,
S5PC110_GPIO_H16,
S5PC110_GPIO_H17,
S5PC110_GPIO_H20,
S5PC110_GPIO_H21,
S5PC110_GPIO_H22,
S5PC110_GPIO_H23,
S5PC110_GPIO_H24,
S5PC110_GPIO_H25,
S5PC110_GPIO_H26,
S5PC110_GPIO_H27,
S5PC110_GPIO_H30,
S5PC110_GPIO_H31,
S5PC110_GPIO_H32,
S5PC110_GPIO_H33,
S5PC110_GPIO_H34,
S5PC110_GPIO_H35,
S5PC110_GPIO_H36,
S5PC110_GPIO_H37,
S5PC110_GPIO_MAX_PORT
};
/* functions */
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
struct gpio_info {
unsigned int reg_addr; /* Address of register for this part */
unsigned int max_gpio; /* Maximum GPIO in this part */
};
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
#define S5PC100_GPIO_NUM_PARTS 1
static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = {
{ S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT },
};
#define S5P_GPIO_PART_SHIFT (24)
#define S5P_GPIO_PART_MASK (0xff)
#define S5P_GPIO_BANK_SHIFT (8)
#define S5P_GPIO_BANK_MASK (0xffff)
#define S5P_GPIO_PIN_MASK (0xff)
#define S5PC110_GPIO_NUM_PARTS 1
static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = {
{ S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT },
};
#define S5P_GPIO_SET_PART(x) \
(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_s5pc100())
return s5pc100_gpio_data;
else if (cpu_is_s5pc110())
return s5pc110_gpio_data;
#define S5P_GPIO_GET_PART(x) \
(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
return NULL;
}
#define S5P_GPIO_SET_PIN(x) \
((x) & S5P_GPIO_PIN_MASK)
static inline unsigned int get_bank_num(void)
{
if (cpu_is_s5pc100())
return S5PC100_GPIO_NUM_PARTS;
else if (cpu_is_s5pc110())
return S5PC110_GPIO_NUM_PARTS;
#define S5PC100_SET_BANK(bank) \
(((unsigned)&(((struct s5pc100_gpio *) \
S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
return 0;
}
#define S5PC110_SET_BANK(bank) \
((((unsigned)&(((struct s5pc110_gpio *) \
S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
/*
* This structure helps mapping symbolic GPIO names into indices from
* exynos5_gpio_pin/exynos5420_gpio_pin enums.
*
* By convention, symbolic GPIO name is defined as follows:
*
* g[p]<bank><set><bit>, where
* p is optional
* <bank> - a single character bank name, as defined by the SOC
* <set> - a single digit set number
* <bit> - bit number within the set (in 0..7 range).
*
* <set><bit> essentially form an octal number of the GPIO pin within the bank
* space. On the 5420 architecture some banks' sets do not start not from zero
* ('d' starts from 1 and 'j' starts from 4). To compensate for that and
* maintain flat number space withoout holes, those banks use offsets to be
* deducted from the pin number.
*/
struct gpio_name_num_table {
char bank; /* bank name symbol */
u8 bank_size; /* total number of pins in the bank */
char bank_offset; /* offset of the first bank's pin */
unsigned int base; /* index of the first bank's pin in the enum */
};
#define s5pc100_gpio_get(bank, pin) \
(S5P_GPIO_SET_PART(0) | \
S5PC100_SET_BANK(bank) | \
S5P_GPIO_SET_PIN(pin))
#define GPIO_PER_BANK 8
#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
static const struct gpio_name_num_table s5pc100_gpio_table[] = {
GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0),
GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0),
GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0),
GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0),
GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0),
GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0),
GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0),
GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0),
GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0),
GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0),
GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0),
GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0),
{ 0 }
};
#define s5pc110_gpio_get(bank, pin) \
(S5P_GPIO_SET_PART(0) | \
S5PC110_SET_BANK(bank) | \
S5P_GPIO_SET_PIN(pin))
static const struct gpio_name_num_table s5pc110_gpio_table[] = {
GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0),
GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0),
GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0),
GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0),
GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0),
GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0),
GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0),
GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0),
GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0),
GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0),
{ 0 }
};
static inline unsigned int s5p_gpio_base(int nr)
{
return samsung_get_base_gpio();
}
/* functions */
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
int gpio_direction_output(unsigned gpio, int value);
int gpio_set_value(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
void gpio_set_rate(int gpio, int mode);
struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
int s5p_gpio_get_pin(unsigned gpio);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
#endif
/* Pin configurations */
#define GPIO_INPUT 0x0
#define GPIO_OUTPUT 0x1
#define GPIO_IRQ 0xf
#define GPIO_FUNC(x) (x)
#define S5P_GPIO_INPUT 0x0
#define S5P_GPIO_OUTPUT 0x1
#define S5P_GPIO_IRQ 0xf
#define S5P_GPIO_FUNC(x) (x)
/* Pull mode */
#define GPIO_PULL_NONE 0x0
#define GPIO_PULL_DOWN 0x1
#define GPIO_PULL_UP 0x2
#define S5P_GPIO_PULL_NONE 0x0
#define S5P_GPIO_PULL_DOWN 0x1
#define S5P_GPIO_PULL_UP 0x2
/* Drive Strength level */
#define GPIO_DRV_1X 0x0
#define GPIO_DRV_3X 0x1
#define GPIO_DRV_2X 0x2
#define GPIO_DRV_4X 0x3
#define GPIO_DRV_FAST 0x0
#define GPIO_DRV_SLOW 0x1
#define S5P_GPIO_DRV_1X 0x0
#define S5P_GPIO_DRV_3X 0x1
#define S5P_GPIO_DRV_2X 0x2
#define S5P_GPIO_DRV_4X 0x3
#define S5P_GPIO_DRV_FAST 0x0
#define S5P_GPIO_DRV_SLOW 0x1
#endif

11
board/samsung/arndale/arndale.c
Unescape View File

@ -16,17 +16,14 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_EHCI_EXYNOS
int board_usb_init(int index, enum usb_init_type init)
{
struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
/* Configure gpios for usb 3503 hub:
* disconnect, toggle reset and connect
*/
s5p_gpio_direction_output(&gpio->d1, 7, 0);
s5p_gpio_direction_output(&gpio->x3, 5, 0);
gpio_direction_output(EXYNOS5_GPIO_D17, 0);
gpio_direction_output(EXYNOS5_GPIO_X35, 0);
s5p_gpio_direction_output(&gpio->x3, 5, 1);
s5p_gpio_direction_output(&gpio->d1, 7, 1);
gpio_direction_output(EXYNOS5_GPIO_X35, 1);
gpio_direction_output(EXYNOS5_GPIO_D17, 1);
return 0;
}

32
board/samsung/goni/goni.c
Unescape View File

@ -17,8 +17,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct s5pc110_gpio *s5pc110_gpio;
u32 get_board_rev(void)
{
return 0;
@ -27,8 +25,6 @@ u32 get_board_rev(void)
int board_init(void)
{
/* Set Initial global variables */
s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE;
gd->bd->bi_arch_number = MACH_TYPE_GONI;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@ -82,7 +78,7 @@ int board_mmc_init(bd_t *bis)
int i, ret, ret_sd = 0;
/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
gpio_direction_output(S5PC110_GPIO_J27, 1);
/*
* MMC0 GPIO
@ -91,15 +87,15 @@ int board_mmc_init(bd_t *bis)
* GPG0[2] SD_0_CDn -> Not used
* GPG0[3:6] SD_0_DATA[0:3]
*/
for (i = 0; i < 7; i++) {
if (i == 2)
for (i = S5PC110_GPIO_G00; i < S5PC110_GPIO_G07; i++) {
if (i == S5PC110_GPIO_G02)
continue;
/* GPG0[0:6] special function 2 */
s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
gpio_cfg_pin(i, 0x2);
/* GPG0[0:6] pull disable */
s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* GPG0[0:6] drv 4x */
s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
ret = s5p_mmc_init(0, 4);
@ -110,20 +106,20 @@ int board_mmc_init(bd_t *bis)
* SD card (T_FLASH) detect and init
* T_FLASH_DETECT: EINT28: GPH3[4] input mode
*/
s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT);
s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP);
gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT);
gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP);
if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) {
for (i = 0; i < 7; i++) {
if (i == 2)
if (!gpio_get_value(S5PC110_GPIO_H34)) {
for (i = S5PC110_GPIO_G20; i < S5PC110_GPIO_G27; i++) {
if (i == S5PC110_GPIO_G22)
continue;
/* GPG2[0:6] special function 2 */
s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2);
gpio_cfg_pin(i, 0x2);
/* GPG2[0:6] pull disable */
s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* GPG2[0:6] drv 4x */
s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
ret_sd = s5p_mmc_init(2, 4);

20
board/samsung/smdk5250/exynos5-dt.c
Unescape View File

@ -27,12 +27,9 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
/* Enable MAX98095 Codec */
s5p_gpio_direction_output(&gpio1->x1, 7, 1);
s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
gpio_direction_output(EXYNOS5_GPIO_X17, 1);
gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
}
#endif
@ -47,19 +44,16 @@ int exynos_init(void)
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
/* For Backlight */
s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->b2, 0, 1);
gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->x1, 5, 1);
gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)

19
board/samsung/smdk5250/smdk5250.c
Unescape View File

@ -29,12 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
/* Enable MAX98095 Codec */
s5p_gpio_direction_output(&gpio1->x1, 7, 1);
s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
gpio_direction_output(EXYNOS5_GPIO_X17, 1);
gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
}
#endif
@ -275,19 +272,17 @@ int exynos_power_init(void)
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
/* For Backlight */
s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->b2, 0, 1);
gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->x1, 5, 1);
gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)

15
board/samsung/smdk5420/smdk5420.c
Unescape View File

@ -21,11 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_EHCI_EXYNOS
static int board_usb_vbus_init(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
/* Enable VBUS power switch */
s5p_gpio_direction_output(&gpio1->x2, 6, 1);
gpio_direction_output(EXYNOS5420_GPIO_X26, 1);
/* VBUS turn ON time */
mdelay(3);
@ -49,15 +46,15 @@ void cfg_lcd_gpio(void)
(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
/* For Backlight */
s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->b2, 0, 1);
gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5420_GPIO_B20, 1);
/* LCD power on */
s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->x1, 5, 1);
gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5420_GPIO_X15, 1);
/* Set Hotplug detect for DP */
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
vidinfo_t panel_info = {

5
board/samsung/smdkc100/smdkc100.c
Unescape View File

@ -21,11 +21,8 @@ static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
struct s5pc100_gpio *const gpio =
(struct s5pc100_gpio *)samsung_get_base_gpio();
/* gpio configuration GPK0CON */
s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);

19
board/samsung/smdkv310/smdkv310.c
Unescape View File

@ -15,15 +15,13 @@
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
struct exynos4_gpio_part1 *gpio1;
struct exynos4_gpio_part2 *gpio2;
static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
/* gpio configuration GPK0CON */
s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
@ -38,9 +36,6 @@ static void smc9115_pre_init(void)
int board_init(void)
{
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
smc9115_pre_init();
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
@ -103,21 +98,21 @@ int board_mmc_init(bd_t *bis)
* GPK2[2] SD_2_CDn
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
for (i = 0; i < 7; i++) {
for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
/* GPK2[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
/* GPK2[0:6] drv 4x */
s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
/* GPK2[0:1] pull disable */
if (i == 0 || i == 1) {
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
continue;
}
/* GPK2[2:6] pull up */
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
gpio_set_pull(i, S5P_GPIO_PULL_UP);
}
err = s5p_mmc_init(2, 4);
return err;

39
board/samsung/trats/trats.c
Unescape View File

@ -54,8 +54,6 @@ int exynos_init(void)
void i2c_init_board(void)
{
int err;
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
/* I2C_5 -> PMIC */
err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
@ -65,8 +63,8 @@ void i2c_init_board(void)
}
/* I2C_8 -> FG */
s5p_gpio_direction_output(&gpio2->y4, 0, 1);
s5p_gpio_direction_output(&gpio2->y4, 1, 1);
gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
}
static void trats_low_power_mode(void)
@ -347,21 +345,19 @@ int exynos_power_init(void)
static unsigned int get_hw_revision(void)
{
struct exynos4_gpio_part1 *gpio =
(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
int hwrev = 0;
int i;
/* hw_rev[3:0] == GPE1[3:0] */
for (i = 0; i < 4; i++) {
s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
for (i = EXYNOS4_GPIO_E10; i < EXYNOS4_GPIO_E14; i++) {
gpio_cfg_pin(i, S5P_GPIO_INPUT);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
}
udelay(1);
for (i = 0; i < 4; i++)
hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
debug("hwrev 0x%x\n", hwrev);
@ -444,11 +440,8 @@ int usb_cable_connected(void)
static void pmic_reset(void)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
s5p_gpio_direction_output(&gpio->x0, 7, 1);
s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
gpio_direction_output(EXYNOS4_GPIO_X07, 1);
gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
}
static void board_clock_init(void)
@ -525,12 +518,9 @@ static void board_power_init(void)
static void exynos_uart_init(void)
{
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
s5p_gpio_direction_output(&gpio2->y4, 7, 1);
gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
}
int exynos_early_init_f(void)
@ -546,14 +536,11 @@ int exynos_early_init_f(void)
void exynos_reset_lcd(void)
{
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
s5p_gpio_direction_output(&gpio2->y4, 5, 1);
gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
udelay(10000);
s5p_gpio_direction_output(&gpio2->y4, 5, 0);
gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
udelay(10000);
s5p_gpio_direction_output(&gpio2->y4, 5, 1);
gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
}
int lcd_power(void)

74
board/samsung/trats2/trats2.c
Unescape View File

@ -25,9 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct exynos4x12_gpio_part1 *gpio1;
static struct exynos4x12_gpio_part2 *gpio2;
static unsigned int board_rev = -1;
static inline u32 get_model_rev(void);
@ -37,26 +34,24 @@ static void check_hw_revision(void)
int modelrev = 0;
int i;
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/*
* GPM1[1:0]: MODEL_REV[1:0]
* Don't set as pull-none for these N/C pin.
* TRM say that it may cause unexcepted state and leakage current.
* and pull-none is only for output function.
*/
for (i = 0; i < 2; i++)
s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
for (i = EXYNOS4X12_GPIO_M10; i < EXYNOS4X12_GPIO_M12; i++)
gpio_cfg_pin(i, S5P_GPIO_INPUT);
/* GPM1[5:2]: HW_REV[3:0] */
for (i = 2; i < 6; i++) {
s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE);
for (i = EXYNOS4X12_GPIO_M12; i < EXYNOS4X12_GPIO_M16; i++) {
gpio_cfg_pin(i, S5P_GPIO_INPUT);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
}
/* GPM1[1:0]: MODEL_REV[1:0] */
for (i = 0; i < 2; i++)
modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i);
modelrev |= (gpio_get_value(EXYNOS4X12_GPIO_M10 + i) << i);
/* board_rev[15:8] = model */
board_rev = modelrev << 8;
@ -74,26 +69,24 @@ static inline u32 get_model_rev(void)
static void board_external_gpio_init(void)
{
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/*
* some pins which in alive block are connected with external pull-up
* but it's default setting is pull-down.
* if that pin set as input then that floated
*/
s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */
s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */
s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/
s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */
s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */
s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */
s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */
s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */
s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */
s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */
s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */
gpio_set_pull(EXYNOS4X12_GPIO_X02, S5P_GPIO_PULL_NONE); /* PS_ALS_INT */
gpio_set_pull(EXYNOS4X12_GPIO_X04, S5P_GPIO_PULL_NONE); /* TSP_nINT */
gpio_set_pull(EXYNOS4X12_GPIO_X07, S5P_GPIO_PULL_NONE); /* AP_PMIC_IRQ*/
gpio_set_pull(EXYNOS4X12_GPIO_X15, S5P_GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
gpio_set_pull(EXYNOS4X12_GPIO_X20, S5P_GPIO_PULL_NONE); /* VOL_UP */
gpio_set_pull(EXYNOS4X12_GPIO_X21, S5P_GPIO_PULL_NONE); /* VOL_DOWN */
gpio_set_pull(EXYNOS4X12_GPIO_X23, S5P_GPIO_PULL_NONE); /* FUEL_ALERT */
gpio_set_pull(EXYNOS4X12_GPIO_X24, S5P_GPIO_PULL_NONE); /* ADC_INT */
gpio_set_pull(EXYNOS4X12_GPIO_X27, S5P_GPIO_PULL_NONE); /* nPOWER */
gpio_set_pull(EXYNOS4X12_GPIO_X30, S5P_GPIO_PULL_NONE); /* WPC_INT */
gpio_set_pull(EXYNOS4X12_GPIO_X35, S5P_GPIO_PULL_NONE); /* OK_KEY */
gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE); /* HDMI_HPD */
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
@ -101,9 +94,6 @@ static void board_init_i2c(void)
{
int err;
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/* I2C_7 */
err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
if (err) {
@ -112,12 +102,12 @@ static void board_init_i2c(void)
}
/* I2C_8 */
s5p_gpio_direction_output(&gpio1->f1, 4, 1);
s5p_gpio_direction_output(&gpio1->f1, 5, 1);
gpio_direction_output(EXYNOS4X12_GPIO_F14, 1);
gpio_direction_output(EXYNOS4X12_GPIO_F15, 1);
/* I2C_9 */
s5p_gpio_direction_output(&gpio2->m2, 1, 1);
s5p_gpio_direction_output(&gpio2->m2, 0, 1);
gpio_direction_output(EXYNOS4X12_GPIO_M21, 1);
gpio_direction_output(EXYNOS4X12_GPIO_M20, 1);
}
#endif
@ -125,17 +115,17 @@ static void board_init_i2c(void)
int get_soft_i2c_scl_pin(void)
{
if (I2C_ADAP_HWNR)
return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */
return EXYNOS4X12_GPIO_M21; /* I2C9 */
else
return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */
return EXYNOS4X12_GPIO_F14; /* I2C8 */
}
int get_soft_i2c_sda_pin(void)
{
if (I2C_ADAP_HWNR)
return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */
return EXYNOS4X12_GPIO_M20; /* I2C9 */
else
return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */
return EXYNOS4X12_GPIO_F15; /* I2C8 */
}
#endif
@ -398,11 +388,9 @@ void exynos_lcd_power_on(void)
{
struct pmic *p = pmic_get("MAX77686_PMIC");
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
/* LCD_2.2V_EN: GPC0[1] */
s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP);
s5p_gpio_direction_output(&gpio1->c0, 1, 1);
gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP);
gpio_direction_output(EXYNOS4X12_GPIO_C01, 1);
/* LDO25 VCC_3.1V_LCD */
pmic_probe(p);
@ -412,12 +400,10 @@ void exynos_lcd_power_on(void)
void exynos_reset_lcd(void)
{
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
/* reset lcd */
s5p_gpio_direction_output(&gpio1->f2, 1, 0);
gpio_direction_output(EXYNOS4X12_GPIO_F21, 0);
udelay(10);
s5p_gpio_set_value(&gpio1->f2, 1, 1);
gpio_set_value(EXYNOS4X12_GPIO_F21, 1);
}
void exynos_lcd_misc_init(vidinfo_t *vid)

51
board/samsung/universal_c210/universal.c
Unescape View File

@ -27,8 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
struct exynos4_gpio_part1 *gpio1;
struct exynos4_gpio_part2 *gpio2;
unsigned int board_rev;
u32 get_board_rev(void)
@ -312,35 +310,35 @@ void exynos_cfg_lcd_gpio(void)
for (i = 0; i < 8; i++) {
/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
}
for (i = 0; i < f3_end; i++) {
for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
}
/* gpio pad configuration for LCD reset. */
s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
spi_init();
}
@ -352,11 +350,11 @@ int mipi_power(void)
void exynos_reset_lcd(void)
{
s5p_gpio_set_value(&gpio2->y4, 5, 1);
gpio_set_value(EXYNOS4_GPIO_Y45, 1);
udelay(10000);
s5p_gpio_set_value(&gpio2->y4, 5, 0);
gpio_set_value(EXYNOS4_GPIO_Y45, 0);
udelay(10000);
s5p_gpio_set_value(&gpio2->y4, 5, 1);
gpio_set_value(EXYNOS4_GPIO_Y45, 1);
udelay(100);
}
@ -386,9 +384,6 @@ void exynos_enable_ldo(unsigned int onoff)
int exynos_init(void)
{
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
switch (get_hwrev()) {
@ -399,7 +394,7 @@ int exynos_init(void)
* you should set it HIGH since it removes the inverter
*/
/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
s5p_gpio_direction_output(&gpio1->e3, 6, 0);
gpio_direction_output(EXYNOS4_GPIO_E36, 0);
break;
default:
/*
@ -407,7 +402,7 @@ int exynos_init(void)
* But set it as HIGH to ensure
*/
/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
s5p_gpio_direction_output(&gpio1->e1, 3, 1);
gpio_direction_output(EXYNOS4_GPIO_E13, 1);
break;
}

204
drivers/gpio/s5p_gpio.c
Unescape View File

@ -8,11 +8,9 @@
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#define S5P_GPIO_GET_BANK(x) ((x >> S5P_GPIO_BANK_SHIFT) \
& S5P_GPIO_BANK_MASK)
#define S5P_GPIO_GET_PIN(x) (x & S5P_GPIO_PIN_MASK)
#define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK)
#define CON_MASK(x) (0xf << ((x) << 2))
#define CON_SFR(x, v) ((v) << ((x) << 2))
@ -28,7 +26,103 @@
#define RATE_MASK(x) (0x1 << (x + 16))
#define RATE_SET(x) (0x1 << (x + 16))
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
#define name_to_gpio(n) s5p_name_to_gpio(n)
static inline int s5p_name_to_gpio(const char *name)
{
unsigned num, irregular_set_number, irregular_bank_base;
const struct gpio_name_num_table *tabp;
char this_bank, bank_name, irregular_bank_name;
char *endp;
/*
* The gpio name starts with either 'g' or 'gp' followed by the bank
* name character. Skip one or two characters depending on the prefix.
*/
if (name[0] == 'g' && name[1] == 'p')
name += 2;
else if (name[0] == 'g')
name++;
else
return -1; /* Name must start with 'g' */
bank_name = *name++;
if (!*name)
return -1; /* At least one digit is required/expected. */
/*
* On both exynos5 and exynos5420 architectures there is a bank of
* GPIOs which does not fall into the regular address pattern. Those
* banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
* assignments help to handle these irregularities.
*/
#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
if (cpu_is_exynos5()) {
if (proid_is_exynos5420()) {
tabp = exynos5420_gpio_table;
irregular_bank_name = 'y';
irregular_set_number = '7';
irregular_bank_base = EXYNOS5420_GPIO_Y70;
} else {
tabp = exynos5_gpio_table;
irregular_bank_name = 'c';
irregular_set_number = '4';
irregular_bank_base = EXYNOS5_GPIO_C40;
}
} else {
if (proid_is_exynos4412())
tabp = exynos4x12_gpio_table;
else
tabp = exynos4_gpio_table;
irregular_bank_name = 0;
irregular_set_number = 0;
irregular_bank_base = 0;
}
#else
if (cpu_is_s5pc110())
tabp = s5pc110_gpio_table;
else
tabp = s5pc100_gpio_table;
irregular_bank_name = 0;
irregular_set_number = 0;
irregular_bank_base = 0;
#endif
this_bank = tabp->bank;
do {
if (bank_name == this_bank) {
unsigned pin_index; /* pin number within the bank */
if ((bank_name == irregular_bank_name) &&
(name[0] == irregular_set_number)) {
pin_index = name[1] - '0';
/* Irregular sets have 8 pins. */
if (pin_index >= GPIO_PER_BANK)
return -1;
num = irregular_bank_base + pin_index;
} else {
pin_index = simple_strtoul(name, &endp, 8);
pin_index -= tabp->bank_offset;
/*
* Sanity check: bunk 'z' has no set number,
* for all other banks there must be exactly
* two octal digits, and the resulting number
* should not exceed the number of pins in the
* bank.
*/
if (((bank_name != 'z') && !name[1]) ||
*endp ||
(pin_index >= tabp->bank_size))
return -1;
num = tabp->base + pin_index;
}
return num;
}
this_bank = (++tabp)->bank;
} while (this_bank);
return -1;
}
static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
{
unsigned int value;
@ -38,18 +132,7 @@ void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
writel(value, &bank->con);
}
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en)
{
s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
s5p_gpio_set_value(bank, gpio, en);
}
void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
{
s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT);
}
void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
{
unsigned int value;
@ -60,7 +143,19 @@ void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
writel(value, &bank->dat);
}
unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank,
int gpio, int en)
{
s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
s5p_gpio_set_value(bank, gpio, en);
}
static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
{
s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
}
static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
{
unsigned int value;
@ -68,7 +163,7 @@ unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
return !!(value & DAT_MASK(gpio));
}
void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
{
unsigned int value;
@ -76,8 +171,8 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
value &= ~PULL_MASK(gpio);
switch (mode) {
case GPIO_PULL_DOWN:
case GPIO_PULL_UP:
case S5P_GPIO_PULL_DOWN:
case S5P_GPIO_PULL_UP:
value |= PULL_MODE(gpio, mode);
break;
default:
@ -87,7 +182,7 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
writel(value, &bank->pull);
}
void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
{
unsigned int value;
@ -95,10 +190,10 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
value &= ~DRV_MASK(gpio);
switch (mode) {
case GPIO_DRV_1X:
case GPIO_DRV_2X:
case GPIO_DRV_3X:
case GPIO_DRV_4X:
case S5P_GPIO_DRV_1X:
case S5P_GPIO_DRV_2X:
case S5P_GPIO_DRV_3X:
case S5P_GPIO_DRV_4X:
value |= DRV_SET(gpio, mode);
break;
default:
@ -108,7 +203,7 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
writel(value, &bank->drv);
}
void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
{
unsigned int value;
@ -116,8 +211,8 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
value &= ~RATE_MASK(gpio);
switch (mode) {
case GPIO_DRV_FAST:
case GPIO_DRV_SLOW:
case S5P_GPIO_DRV_FAST:
case S5P_GPIO_DRV_SLOW:
value |= RATE_SET(gpio);
break;
default:
@ -127,12 +222,31 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
writel(value, &bank->drv);
}
struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
{
unsigned bank = S5P_GPIO_GET_BANK(gpio);
unsigned base = s5p_gpio_base(gpio);
const struct gpio_info *data;
unsigned int upto;
int i, count;
data = get_gpio_data();
count = get_bank_num();
upto = 0;
for (i = 0; i < count; i++) {
debug("i=%d, upto=%d\n", i, upto);
if (gpio < data->max_gpio) {
struct s5p_gpio_bank *bank;
bank = (struct s5p_gpio_bank *)data->reg_addr;
bank += (gpio - upto) / GPIO_PER_BANK;
debug("gpio=%d, bank=%p\n", gpio, bank);
return bank;
}
upto = data->max_gpio;
data++;
}
return (struct s5p_gpio_bank *)(base + bank);
return NULL;
}
int s5p_gpio_get_pin(unsigned gpio)
@ -179,3 +293,27 @@ int gpio_set_value(unsigned gpio, int value)
return 0;
}
void gpio_set_pull(int gpio, int mode)
{
s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
s5p_gpio_get_pin(gpio), mode);
}
void gpio_set_drv(int gpio, int mode)
{
s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
s5p_gpio_get_pin(gpio), mode);
}
void gpio_cfg_pin(int gpio, int cfg)
{
s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
s5p_gpio_get_pin(gpio), cfg);
}
void gpio_set_rate(int gpio, int mode)
{
s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
s5p_gpio_get_pin(gpio), mode);
}

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