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powerpc: mpc5xxx: remove BC3450 board support

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This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
master
Masahiro Yamada 10 years ago committed by Tom Rini
parent e52e9cc77f
commit f8296d6975
10 changed files with 8 additions and 1987 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      arch/powerpc/cpu/mpc5xxx/Kconfig
  2. 9
      board/bc3450/Kconfig
  3. 6
      board/bc3450/MAINTAINERS
  4. 8
      board/bc3450/Makefile
  5. 586
      board/bc3450/bc3450.c
  6. 805
      board/bc3450/cmd_bc3450.c
  7. 18
      board/bc3450/mt48lc16m16a2-75.h
  8. 3
      configs/BC3450_defconfig
  9. 15
      doc/README.scrapyard
  10. 541
      include/configs/BC3450.h

4
arch/powerpc/cpu/mpc5xxx/Kconfig
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@ -14,9 +14,6 @@ config TARGET_A3M071
config TARGET_A4M072
bool "Support a4m072"
config TARGET_BC3450
bool "Support BC3450"
config TARGET_CANMB
bool "Support canmb"
@ -84,7 +81,6 @@ endchoice
source "board/a3m071/Kconfig"
source "board/a4m072/Kconfig"
source "board/bc3450/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
source "board/galaxy5200/Kconfig"

9
board/bc3450/Kconfig
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@ -1,9 +0,0 @@
if TARGET_BC3450
config SYS_BOARD
default "bc3450"
config SYS_CONFIG_NAME
default "BC3450"
endif

6
board/bc3450/MAINTAINERS
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@ -1,6 +0,0 @@
BC3450 BOARD
#M: -
S: Maintained
F: board/bc3450/
F: include/configs/BC3450.h
F: configs/BC3450_defconfig

8
board/bc3450/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := bc3450.o cmd_bc3450.o

586
board/bc3450/bc3450.c
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@ -1,586 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2004-2005
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* (C) Copyright 2006
* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <netdev.h>
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
#endif
#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m16a2-75.h"
#endif
#ifdef CONFIG_RTC_MPC5200
#include <rtc.h>
#endif
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
sdram_start(1);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
__builtin_ffs(dramsize >> 20) - 1;
} else {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
}
/* let SDRAM CS1 start right after CS0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
sdram_start(1);
test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else {
dramsize2 = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20)) {
dramsize2 = 0;
}
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
} else {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
}
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13) {
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
} else {
dramsize2 = 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
return dramsize;
}
int checkboard (void)
{
#if defined (CONFIG_TQM5200)
puts ("Board: TQM5200 (TQ-Components GmbH)\n");
#endif
#if defined (CONFIG_BC3450)
puts ("Dev: GERSYS BC3450\n");
#endif
return 0;
}
void flash_preinit(void)
{
/*
* Now, when we are in RAM, enable flash write
* access for detection process.
* Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
}
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
if (idereset) {
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
} else {
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
}
#endif
#ifdef CONFIG_POST
/*
* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
* is left open, no keypress is detected.
*/
int post_hotkeys_pressed(void)
{
struct mpc5xxx_gpio *gpio;
gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
/*
* Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
* CODEC or UART mode. Consumer IrDA should still be possible.
*/
gpio->port_config &= ~(0x07000000);
gpio->port_config |= 0x03000000;
/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
gpio->simple_gpioe |= 0x20000000;
/* Configure GPIO_IRDA_1 as input */
gpio->simple_ddr &= ~(0x20000000);
return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
#ifdef CONFIG_RTC_MPC5200
struct rtc_time t;
/* set to Wed Dec 31 19:00:00 1969 */
t.tm_sec = t.tm_min = 0;
t.tm_hour = 19;
t.tm_mday = 31;
t.tm_mon = 12;
t.tm_year = 1969;
t.tm_wday = 3;
rtc_set(&t);
#endif /* CONFIG_RTC_MPC5200 */
#ifdef CONFIG_PS2MULT
ps2mult_early_init();
#endif /* CONFIG_PS2MULT */
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */
int last_stage_init (void)
{
/*
* auto scan for really existing devices and re-set chip select
* configuration.
*/
u16 save, tmp;
int restore;
/*
* Check for SRAM and SRAM size
*/
/* save original SRAM content */
save = *(volatile u16 *)CONFIG_SYS_CS2_START;
restore = 1;
/* write test pattern to SRAM */
*(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
__asm__ volatile ("sync");
/*
* Put a different pattern on the data lines: otherwise they may float
* long enough to read back what we wrote.
*/
tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
if (tmp == 0xA5A5)
puts ("!! possible error in SRAM detection\n");
if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
/* no SRAM at all, disable cs */
*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
restore = 0;
__asm__ volatile ("sync");
} else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
/* make sure that we access a mirrored address */
*(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
__asm__ volatile ("sync");
if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
/* SRAM size = 512 kByte */
*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
0x80000);
__asm__ volatile ("sync");
puts ("SRAM: 512 kB\n");
}
else
puts ("!! possible error in SRAM detection\n");
} else {
puts ("SRAM: 1 MB\n");
}
/* restore origianl SRAM content */
if (restore) {
*(volatile u16 *)CONFIG_SYS_CS2_START = save;
__asm__ volatile ("sync");
}
/*
* Check for Grafic Controller
*/
/* save origianl FB content */
save = *(volatile u16 *)CONFIG_SYS_CS1_START;
restore = 1;
/* write test pattern to FB memory */
*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
__asm__ volatile ("sync");
/*
* Put a different pattern on the data lines: otherwise they may float
* long enough to read back what we wrote.
*/
tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
if (tmp == 0xA5A5)
puts ("!! possible error in grafic controller detection\n");
if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
/* no grafic controller at all, disable cs */
*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
restore = 0;
__asm__ volatile ("sync");
} else {
puts ("VGA: SMI501 (Voyager) with 8 MB\n");
}
/* restore origianl FB content */
if (restore) {
*(volatile u16 *)CONFIG_SYS_CS1_START = save;
__asm__ volatile ("sync");
}
return 0;
}
#ifdef CONFIG_VIDEO_SM501
#define DISPLAY_WIDTH 640
#define DISPLAY_HEIGHT 480
#ifdef CONFIG_VIDEO_SM501_8BPP
#error CONFIG_VIDEO_SM501_8BPP not supported.
#endif /* CONFIG_VIDEO_SM501_8BPP */
#ifdef CONFIG_VIDEO_SM501_16BPP
#error CONFIG_VIDEO_SM501_16BPP not supported.
#endif /* CONFIG_VIDEO_SM501_16BPP */
#ifdef CONFIG_VIDEO_SM501_32BPP
static const SMI_REGS init_regs [] =
{
#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
/* FP only */
{0x00004, 0x0},
{0x00048, 0x00021807},
{0x0004C, 0x091a0a01},
{0x00054, 0x1},
{0x00040, 0x00021807},
{0x00044, 0x091a0a01},
{0x00054, 0x0},
{0x80000, 0x01013106},
{0x80004, 0xc428bb17},
{0x80000, 0x03013106},
{0x8000C, 0x00000000},
{0x80010, 0x0a000a00},
{0x80014, 0x02800000},
{0x80018, 0x01e00000},
{0x8001C, 0x00000000},
{0x80020, 0x01e00280},
{0x80024, 0x02fa027f},
{0x80028, 0x004a028b},
{0x8002C, 0x020c01df},
{0x80030, 0x000201e9},
{0x80200, 0x00010200},
{0x80000, 0x0f013106},
#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
/* CRT only */
{0x00004, 0x0},
{0x00048, 0x00021807},
{0x0004C, 0x10090a01},
{0x00054, 0x1},
{0x00040, 0x00021807},
{0x00044, 0x10090a01},
{0x00054, 0x0},
{0x80200, 0x00010000},
{0x80204, 0x0},
{0x80208, 0x0A000A00},
{0x8020C, 0x02fa027f},
{0x80210, 0x004a028b},
{0x80214, 0x020c01df},
{0x80218, 0x000201e9},
{0x80200, 0x00013306},
#else /* panel + CRT */
{0x00004, 0x0},
{0x00048, 0x00021807},
{0x0004C, 0x091a0a01},
{0x00054, 0x1},
{0x00040, 0x00021807},
{0x00044, 0x091a0a01},
{0x00054, 0x0},
{0x80000, 0x0f013106},
{0x80004, 0xc428bb17},
{0x8000C, 0x00000000},
{0x80010, 0x0a000a00},
{0x80014, 0x02800000},
{0x80018, 0x01e00000},
{0x8001C, 0x00000000},
{0x80020, 0x01e00280},
{0x80024, 0x02fa027f},
{0x80028, 0x004a028b},
{0x8002C, 0x020c01df},
{0x80030, 0x000201e9},
{0x80200, 0x00010000},
#endif
{0, 0}
};
#endif /* CONFIG_VIDEO_SM501_32BPP */
#ifdef CONFIG_CONSOLE_EXTRA_INFO
/*
* Return text to be printed besides the logo.
*/
void video_get_info_str (int line_number, char *info)
{
if (line_number == 1) {
#if defined (CONFIG_TQM5200)
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
#else
#error No supported board selected
#endif /* CONFIG_TQM5200 */
#if defined (CONFIG_BC3450)
} else if (line_number == 2) {
strcpy (info, " Dev: GERSYS BC3450");
#endif /* CONFIG_BC3450 */
}
else {
info [0] = '\0';
}
}
#endif
/*
* Returns SM501 register base address. First thing called in the
* driver. Checks if SM501 is physically present.
*/
unsigned int board_video_init (void)
{
u16 save, tmp;
int restore, ret;
/*
* Check for Grafic Controller
*/
/* save origianl FB content */
save = *(volatile u16 *)CONFIG_SYS_CS1_START;
restore = 1;
/* write test pattern to FB memory */
*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
__asm__ volatile ("sync");
/*
* Put a different pattern on the data lines: otherwise they may float
* long enough to read back what we wrote.
*/
tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
if (tmp == 0xA5A5)
puts ("!! possible error in grafic controller detection\n");
if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
/* no grafic controller found */
restore = 0;
ret = 0;
} else {
ret = SM501_MMIO_BASE;
}
if (restore) {
*(volatile u16 *)CONFIG_SYS_CS1_START = save;
__asm__ volatile ("sync");
}
return ret;
}
/*
* Returns SM501 framebuffer address
*/
unsigned int board_video_get_fb (void)
{
return SM501_FB_BASE;
}
/*
* Called after initializing the SM501 and before clearing the screen.
*/
void board_validate_screen (unsigned int base)
{
}
/*
* Return a pointer to the initialization sequence.
*/
const SMI_REGS *board_get_regs (void)
{
return init_regs;
}
int board_get_width (void)
{
return DISPLAY_WIDTH;
}
int board_get_height (void)
{
return DISPLAY_HEIGHT;
}
#endif /* CONFIG_VIDEO_SM501 */
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis); /* Built in FEC comes first */
return pci_eth_init(bis);
}

805
board/bc3450/cmd_bc3450.c
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@ -1,805 +0,0 @@
/*
* (C) Copyright 2005
* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
*
* (C) Copyright 2005
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
/*
* BC3450 specific commands
*/
#if defined(CONFIG_CMD_BSP)
/*
* Definitions for DS1620 chip
*/
#define THERM_START_CONVERT 0xee
#define THERM_RESET 0xaf
#define THERM_READ_CONFIG 0xac
#define THERM_READ_TEMP 0xaa
#define THERM_READ_TL 0xa2
#define THERM_READ_TH 0xa1
#define THERM_WRITE_CONFIG 0x0c
#define THERM_WRITE_TL 0x02
#define THERM_WRITE_TH 0x01
#define CONFIG_SYS_1SHOT 1
#define CONFIG_SYS_STANDALONE 0
struct therm {
int hi;
int lo;
};
/*
* SM501 Register
*/
#define SM501_GPIO_CTRL_LOW 0x00000008UL /* gpio pins 0..31 */
#define SM501_GPIO_CTRL_HIGH 0x0000000CUL /* gpio pins 32..63 */
#define SM501_POWER_MODE0_GATE 0x00000040UL
#define SM501_POWER_MODE1_GATE 0x00000048UL
#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
#define SM501_GPIO_DATA_LOW 0x00010000UL
#define SM501_GPIO_DATA_HIGH 0x00010004UL
#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL
#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
#define SM501_CRT_DISPLAY_CONTROL 0x00080200UL
/* SM501 CRT Display Control Bits */
#define SM501_CDC_SEL (1 << 9)
#define SM501_CDC_TE (1 << 8)
#define SM501_CDC_E (1 << 2)
/* SM501 Panel Display Control Bits */
#define SM501_PDC_FPEN (1 << 27)
#define SM501_PDC_BIAS (1 << 26)
#define SM501_PDC_DATA (1 << 25)
#define SM501_PDC_VDDEN (1 << 24)
/* SM501 GPIO Data LOW Bits */
#define SM501_GPIO24 0x01000000
#define SM501_GPIO25 0x02000000
#define SM501_GPIO26 0x04000000
#define SM501_GPIO27 0x08000000
#define SM501_GPIO28 0x10000000
#define SM501_GPIO29 0x20000000
#define SM501_GPIO30 0x40000000
#define SM501_GPIO31 0x80000000
/* SM501 GPIO Data HIGH Bits */
#define SM501_GPIO46 0x00004000
#define SM501_GPIO47 0x00008000
#define SM501_GPIO48 0x00010000
#define SM501_GPIO49 0x00020000
#define SM501_GPIO50 0x00040000
#define SM501_GPIO51 0x00080000
/* BC3450 GPIOs @ SM501 Data LOW */
#define DIP (SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27)
#define DS1620_DQ SM501_GPIO29 /* I/O */
#define DS1620_CLK SM501_GPIO30 /* High active O/P */
#define DS1620_RES SM501_GPIO31 /* Low active O/P */
/* BC3450 GPIOs @ SM501 Data HIGH */
#define BUZZER SM501_GPIO47 /* Low active O/P */
#define DS1620_TLOW SM501_GPIO48 /* High active I/P */
#define PWR_OFF SM501_GPIO49 /* Low active O/P */
#define FP_DATA_TRI SM501_GPIO50 /* High active O/P */
/*
* Initialise GPIO on SM501
*
* This function may be called from several other functions.
* Yet, the initialisation sequence is executed only the first
* time the function is called.
*/
int sm501_gpio_init (void)
{
static int init_done = 0;
if (init_done) {
debug("sm501_gpio_init: nothing to be done.\n");
return 1;
}
/* enable SM501 GPIO control (in both power modes) */
*(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |=
POWER_MODE_GATE_GPIO_PWM_I2C;
*(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |=
POWER_MODE_GATE_GPIO_PWM_I2C;
/* set up default O/Ps */
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
~(DS1620_RES | DS1620_CLK);
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
~(FP_DATA_TRI);
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
(BUZZER | PWR_OFF);
/* configure directions for SM501 GPIO pins */
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &=
~(0x3F << 14);
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &=
~(DIP | DS1620_DQ);
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |=
(DS1620_RES | DS1620_CLK);
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &=
~DS1620_TLOW;
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |=
(PWR_OFF | BUZZER | FP_DATA_TRI);
init_done = 1;
debug("sm501_gpio_init: done.\n");
return 0;
}
/*
* dip - read Config Inputs
*
* read and prints the dip switch
* and/or external config inputs (4bits) 0...0x0F
*/
int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
vu_long rc = 0;
sm501_gpio_init ();
/* read dip switch */
rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
rc = ~rc;
rc &= DIP;
rc = (int) (rc >> 24);
/* plausibility check */
if (rc > 0x0F)
return -1;
printf ("0x%lx\n", rc);
return 0;
}
U_BOOT_CMD (dip, 1, 1, cmd_dip,
"read dip switch and config inputs",
"\n"
" - prints the state of the dip switch and/or\n"
" external configuration inputs as hex value.\n"
" - \"Config 1\" is the LSB");
/*
* buz - turns Buzzer on/off
*/
#ifdef CONFIG_BC3450_BUZZER
static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 2) {
printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
return 1;
}
sm501_gpio_init ();
if (strncmp (argv[1], "on", 2) == 0) {
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
~(BUZZER);
return 0;
} else if (strncmp (argv[1], "off", 3) == 0) {
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
BUZZER;
return 0;
}
printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
return 1;
}
U_BOOT_CMD (buz, 2, 1, cmd_buz,
"turns buzzer on/off",
"\n" "buz <on/off>\n" " - turns the buzzer on or off");
#endif /* CONFIG_BC3450_BUZZER */
/*
* fp - front panel commands
*/
static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
sm501_gpio_init ();
if (strncmp (argv[1], "on", 2) == 0) {
/* turn on VDD first */
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN;
udelay (1000);
/* then put data on */
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA;
/* wait some time and enable backlight */
udelay (1000);
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
udelay (1000);
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
return 0;
} else if (strncmp (argv[1], "off", 3) == 0) {
/* turn off the backlight first */
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
udelay (1000);
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
udelay (200000);
/* wait some time, then remove data */
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
udelay (1000);
/* and remove VDD last */
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) &=
~SM501_PDC_VDDEN;
return 0;
} else if (strncmp (argv[1], "bl", 2) == 0) {
/* turn on/off backlight only */
if (strncmp (argv[2], "on", 2) == 0) {
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) |=
SM501_PDC_BIAS;
udelay (1000);
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) |=
SM501_PDC_FPEN;
return 0;
} else if (strncmp (argv[2], "off", 3) == 0) {
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) &=
~SM501_PDC_FPEN;
udelay (1000);
*(vu_long *) (SM501_MMIO_BASE +
SM501_PANEL_DISPLAY_CONTROL) &=
~SM501_PDC_BIAS;
return 0;
}
}
#ifdef CONFIG_BC3450_CRT
else if (strncmp (argv[1], "crt", 3) == 0) {
/* enables/disables the crt output (debug only) */
if (strncmp (argv[2], "on", 2) == 0) {
*(vu_long *) (SM501_MMIO_BASE +
SM501_CRT_DISPLAY_CONTROL) |=
(SM501_CDC_TE | SM501_CDC_E);
*(vu_long *) (SM501_MMIO_BASE +
SM501_CRT_DISPLAY_CONTROL) &=
~SM501_CDC_SEL;
return 0;
} else if (strncmp (argv[2], "off", 3) == 0) {
*(vu_long *) (SM501_MMIO_BASE +
SM501_CRT_DISPLAY_CONTROL) &=
~(SM501_CDC_TE | SM501_CDC_E);
*(vu_long *) (SM501_MMIO_BASE +
SM501_CRT_DISPLAY_CONTROL) |=
SM501_CDC_SEL;
return 0;
}
}
#endif /* CONFIG_BC3450_CRT */
printf ("Usage:%s\n", cmdtp->help);
return 1;
}
U_BOOT_CMD (fp, 3, 1, cmd_fp,
"front panes access functions",
"\n"
"fp bl <on/off>\n"
" - turns the CCFL backlight of the display on/off\n"
"fp <on/off>\n" " - turns the whole display on/off"
#ifdef CONFIG_BC3450_CRT
"\n"
"fp crt <on/off>\n"
" - enables/disables the crt output (debug only)"
#endif /* CONFIG_BC3450_CRT */
);
/*
* temp - DS1620 thermometer
*/
/* GERSYS BC3450 specific functions */
static inline void bc_ds1620_set_clk (int clk)
{
if (clk)
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
DS1620_CLK;
else
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
~DS1620_CLK;
}
static inline void bc_ds1620_set_data (int dat)
{
if (dat)
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
DS1620_DQ;
else
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
~DS1620_DQ;
}
static inline int bc_ds1620_get_data (void)
{
vu_long rc;
rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
rc &= DS1620_DQ;
if (rc != 0)
rc = 1;
return (int) rc;
}
static inline void bc_ds1620_set_data_dir (int dir)
{
if (dir) /* in */
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
else /* out */
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ;
}
static inline void bc_ds1620_set_reset (int res)
{
if (res)
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES;
else
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
}
/* hardware independent functions */
static void ds1620_send_bits (int nr, int value)
{
int i;
for (i = 0; i < nr; i++) {
bc_ds1620_set_data (value & 1);
bc_ds1620_set_clk (0);
udelay (1);
bc_ds1620_set_clk (1);
udelay (1);
value >>= 1;
}
}
static unsigned int ds1620_recv_bits (int nr)
{
unsigned int value = 0, mask = 1;
int i;
bc_ds1620_set_data (0);
for (i = 0; i < nr; i++) {
bc_ds1620_set_clk (0);
udelay (1);
if (bc_ds1620_get_data ())
value |= mask;
mask <<= 1;
bc_ds1620_set_clk (1);
udelay (1);
}
return value;
}
static void ds1620_out (int cmd, int bits, int value)
{
bc_ds1620_set_clk (1);
bc_ds1620_set_data_dir (0);
bc_ds1620_set_reset (0);
udelay (1);
bc_ds1620_set_reset (1);
udelay (1);
ds1620_send_bits (8, cmd);
if (bits)
ds1620_send_bits (bits, value);
udelay (1);
/* go stand alone */
bc_ds1620_set_data_dir (1);
bc_ds1620_set_reset (0);
bc_ds1620_set_clk (0);
udelay (10000);
}
static unsigned int ds1620_in (int cmd, int bits)
{
unsigned int value;
bc_ds1620_set_clk (1);
bc_ds1620_set_data_dir (0);
bc_ds1620_set_reset (0);
udelay (1);
bc_ds1620_set_reset (1);
udelay (1);
ds1620_send_bits (8, cmd);
bc_ds1620_set_data_dir (1);
value = ds1620_recv_bits (bits);
/* go stand alone */
bc_ds1620_set_data_dir (1);
bc_ds1620_set_reset (0);
bc_ds1620_set_clk (0);
return value;
}
static int cvt_9_to_int (unsigned int val)
{
if (val & 0x100)
val |= 0xfffffe00;
return val;
}
/* set thermostate thresholds */
static void ds1620_write_state (struct therm *therm)
{
ds1620_out (THERM_WRITE_TL, 9, therm->lo);
ds1620_out (THERM_WRITE_TH, 9, therm->hi);
ds1620_out (THERM_START_CONVERT, 0, 0);
}
static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
int i;
struct therm therm;
sm501_gpio_init ();
/* print temperature */
if (argc == 1) {
i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9));
printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
return 0;
}
/* set to default operation */
if (strncmp (argv[1], "set", 3) == 0) {
if (strncmp (argv[2], "default", 3) == 0) {
therm.hi = +88;
therm.lo = -20;
therm.hi <<= 1;
therm.lo <<= 1;
ds1620_write_state (&therm);
ds1620_out (THERM_WRITE_CONFIG, 8, CONFIG_SYS_STANDALONE);
return 0;
}
}
printf ("Usage:%s\n", cmdtp->help);
return 1;
}
U_BOOT_CMD (temp, 3, 1, cmd_temp,
"print current temperature",
"\n" "temp\n" " - print current temperature");
#ifdef CONFIG_BC3450_CAN
/*
* Initialise CAN interface
*
* return 1 on CAN initialization failure
* return 0 if no failure
*/
int can_init (void)
{
static int init_done = 0;
int i;
struct mpc5xxx_mscan *can1 =
(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
struct mpc5xxx_mscan *can2 =
(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
/* GPIO configuration of the CAN pins is done in BC3450.h */
if (!init_done) {
/* init CAN 1 */
can1->canctl1 |= 0x80; /* CAN enable */
udelay (100);
i = 0;
can1->canctl0 |= 0x02; /* sleep mode */
/* wait until sleep mode reached */
while (!(can1->canctl1 & 0x02)) {
udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN1 initialize error, "
"can not enter sleep mode!\n",
__FUNCTION__);
return 1;
}
}
i = 0;
can1->canctl0 = 0x01; /* enter init mode */
/* wait until init mode reached */
while (!(can1->canctl1 & 0x01)) {
udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN1 initialize error, "
"can not enter init mode!\n",
__FUNCTION__);
return 1;
}
}
can1->canctl1 = 0x80;
can1->canctl1 |= 0x40;
can1->canbtr0 = 0x0F;
can1->canbtr1 = 0x7F;
can1->canidac &= ~(0x30);
can1->canidar1 = 0x00;
can1->canidar3 = 0x00;
can1->canidar5 = 0x00;
can1->canidar7 = 0x00;
can1->canidmr0 = 0xFF;
can1->canidmr1 = 0xFF;
can1->canidmr2 = 0xFF;
can1->canidmr3 = 0xFF;
can1->canidmr4 = 0xFF;
can1->canidmr5 = 0xFF;
can1->canidmr6 = 0xFF;
can1->canidmr7 = 0xFF;
i = 0;
can1->canctl0 &= ~(0x01); /* leave init mode */
can1->canctl0 &= ~(0x02);
/* wait until init and sleep mode left */
while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN1 initialize error, "
"can not leave init/sleep mode!\n",
__FUNCTION__);
return 1;
}
}
/* init CAN 2 */
can2->canctl1 |= 0x80; /* CAN enable */
udelay (100);
i = 0;
can2->canctl0 |= 0x02; /* sleep mode */
/* wait until sleep mode reached */
while (!(can2->canctl1 & 0x02)) {
udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN2 initialize error, "
"can not enter sleep mode!\n",
__FUNCTION__);
return 1;
}
}
i = 0;
can2->canctl0 = 0x01; /* enter init mode */
/* wait until init mode reached */
while (!(can2->canctl1 & 0x01)) {
udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN2 initialize error, "
"can not enter init mode!\n",
__FUNCTION__);
return 1;
}
}
can2->canctl1 = 0x80;
can2->canctl1 |= 0x40;
can2->canbtr0 = 0x0F;
can2->canbtr1 = 0x7F;
can2->canidac &= ~(0x30);
can2->canidar1 = 0x00;
can2->canidar3 = 0x00;
can2->canidar5 = 0x00;
can2->canidar7 = 0x00;
can2->canidmr0 = 0xFF;
can2->canidmr1 = 0xFF;
can2->canidmr2 = 0xFF;
can2->canidmr3 = 0xFF;
can2->canidmr4 = 0xFF;
can2->canidmr5 = 0xFF;
can2->canidmr6 = 0xFF;
can2->canidmr7 = 0xFF;
can2->canctl0 &= ~(0x01); /* leave init mode */
can2->canctl0 &= ~(0x02);
i = 0;
/* wait until init mode left */
while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN2 initialize error, "
"can not leave init/sleep mode!\n",
__FUNCTION__);
return 1;
}
}
init_done = 1;
}
return 0;
}
/*
* Do CAN test
* by sending message between CAN1 and CAN2
*
* return 1 on CAN failure
* return 0 if no failure
*/
int do_can (char * const argv[])
{
int i;
struct mpc5xxx_mscan *can1 =
(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
struct mpc5xxx_mscan *can2 =
(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
/* send a message on CAN1 */
can1->cantbsel = 0x01;
can1->cantxfg.idr[0] = 0x55;
can1->cantxfg.idr[1] = 0x00;
can1->cantxfg.idr[1] &= ~0x8;
can1->cantxfg.idr[1] &= ~0x10;
can1->cantxfg.dsr[0] = 0xCC;
can1->cantxfg.dlr = 1;
can1->cantxfg.tbpr = 0;
can1->cantflg = 0x01;
i = 0;
while ((can1->cantflg & 0x01) == 0) {
i++;
if (i == 10) {
printf ("%s: CAN1 send timeout, "
"can not send message!\n", __FUNCTION__);
return 1;
}
udelay (1000);
}
udelay (1000);
i = 0;
while (!(can2->canrflg & 0x01)) {
i++;
if (i == 10) {
printf ("%s: CAN2 receive timeout, "
"no message received!\n", __FUNCTION__);
return 1;
}
udelay (1000);
}
if (can2->canrxfg.dsr[0] != 0xCC) {
printf ("%s: CAN2 receive error, "
"data mismatch!\n", __FUNCTION__);
return 1;
}
/* send a message on CAN2 */
can2->cantbsel = 0x01;
can2->cantxfg.idr[0] = 0x55;
can2->cantxfg.idr[1] = 0x00;
can2->cantxfg.idr[1] &= ~0x8;
can2->cantxfg.idr[1] &= ~0x10;
can2->cantxfg.dsr[0] = 0xCC;
can2->cantxfg.dlr = 1;
can2->cantxfg.tbpr = 0;
can2->cantflg = 0x01;
i = 0;
while ((can2->cantflg & 0x01) == 0) {
i++;
if (i == 10) {
printf ("%s: CAN2 send error, "
"can not send message!\n", __FUNCTION__);
return 1;
}
udelay (1000);
}
udelay (1000);
i = 0;
while (!(can1->canrflg & 0x01)) {
i++;
if (i == 10) {
printf ("%s: CAN1 receive timeout, "
"no message received!\n", __FUNCTION__);
return 1;
}
udelay (1000);
}
if (can1->canrxfg.dsr[0] != 0xCC) {
printf ("%s: CAN1 receive error 0x%02x\n",
__FUNCTION__, (can1->canrxfg.dsr[0]));
return 1;
}
return 0;
}
#endif /* CONFIG_BC3450_CAN */
/*
* test - BC3450 HW test routines
*/
int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_BC3450_CAN
int rcode;
can_init ();
#endif /* CONFIG_BC3450_CAN */
sm501_gpio_init ();
if (argc != 2) {
printf ("Usage:%s\n", cmdtp->help);
return 1;
}
if (strncmp (argv[1], "unit-off", 8) == 0) {
printf ("waiting 2 seconds...\n");
udelay (2000000);
*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
~PWR_OFF;
return 0;
}
#ifdef CONFIG_BC3450_CAN
else if (strncmp (argv[1], "can", 2) == 0) {
rcode = do_can (argv);
if (simple_strtoul (argv[2], NULL, 10) == 2) {
if (rcode == 0)
printf ("OK\n");
else
printf ("Error\n");
}
return rcode;
}
#endif /* CONFIG_BC3450_CAN */
printf ("Usage:%s\n", cmdtp->help);
return 1;
}
U_BOOT_CMD (test, 2, 1, cmd_test, "unit test routines", "\n"
#ifdef CONFIG_BC3450_CAN
"test can\n"
" - connect CAN1 (X8) with CAN2 (X9) for this test\n"
#endif /* CONFIG_BC3450_CAN */
"test unit-off\n"
" - turns off the BC3450 unit\n"
" WARNING: Unsaved environment variables will be lost!"
);
#endif

18
board/bc3450/mt48lc16m16a2-75.h
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@ -1,18 +0,0 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDRAM_DDR 0 /* is SDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
#define SDRAM_CONFIG2 0x8AD70000
/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */

3
configs/BC3450_defconfig
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@ -1,3 +0,0 @@
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_BC3450=y

15
doc/README.scrapyard
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@ -12,13 +12,14 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
hawkboard arm arm926ejs - - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
tnetv107x arm arm1176 - - Chan-Taek Park <c-park@ti.com>
a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
cm41xx arm arm920t - -
dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
BC3450 powerpc mpc5xxx - -
hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
tnetv107x arm arm1176 50b82c4b 2015-02-24 Chan-Taek Park <c-park@ti.com>
a320evb arm arm920t 29fc6f24 2015-02-24 Po-Yu Chuang <ratbert@faraday-tech.com>
cm4008 arm arm920t a2f39e83 2015-02-24 Greg Ungerer <greg.ungerer@opengear.com>
cm41xx arm arm920t a2f39e83 2015-02-24
dkb arm arm926ejs 346cfba4 2015-02-24 Lei Wen <leiwen@marvell.com>
jadecpu arm arm926ejs 41fbbbbc 2015-02-24 Matthias Weisser <weisserm@arcor.de>
icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23
cpci5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>

541
include/configs/BC3450.h
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/*
* -- Version 1.1 --
*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2005
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* (C) Copyright 2005
* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
*
* History:
* 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
#define CONFIG_BC3450_USB 1 /* + USB support */
# define CONFIG_FAT 1 /* + FAT support */
# define CONFIG_EXT2 1 /* + EXT2 support */
#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
#undef CONFIG_BC3450_CAN /* + CAN transceiver */
#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFC000000 boot low (standard configuration with room for
* max 64 MByte Flash ROM)
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFC000000
#endif
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* AT-PS/2 Multiplexer
*/
#ifdef CONFIG_BC3450_PS2
# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
# define CONFIG_BOARD_EARLY_INIT_R
#endif /* CONFIG_BC3450_PS2 */
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
# define CONFIG_PCI 1
# define CONFIG_PCI_PNP 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
/*
* Video console
*/
# define CONFIG_VIDEO
# define CONFIG_VIDEO_SM501
# define CONFIG_VIDEO_SM501_32BPP
# define CONFIG_CFB_CONSOLE
# define CONFIG_VIDEO_LOGO
# define CONFIG_VGA_AS_SINGLE_DEVICE
# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
# define CONFIG_VIDEO_SW_CURSOR
# define CONFIG_SPLASH_SCREEN
# define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
* Partitions
*/
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
/*
* USB
*/
#ifdef CONFIG_BC3450_USB
# define CONFIG_USB_OHCI
# define CONFIG_USB_STORAGE
#endif /* CONFIG_BC3450_USB */
/*
* POST support
*/
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
CONFIG_SYS_POST_CPU | \
CONFIG_SYS_POST_I2C)
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#endif /* CONFIG_POST */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_BSP
#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP
#endif
#ifdef CONFIG_BC3450_IDE
#define CONFIG_CMD_IDE
#endif
#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
#ifdef CONFIG_FAT
#define CONFIG_CMD_FAT
#endif
#ifdef CONFIG_EXT2
#define CONFIG_CMD_EXT2
#endif
#endif
#ifdef CONFIG_BC3450_USB
#define CONFIG_CMD_USB
#endif
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif
#define CONFIG_TIMESTAMP /* display image timestamps */
#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo;"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ipaddr=192.168.1.10\0" \
"serverip=192.168.1.3\0" \
"netmask=255.255.255.0\0" \
"hostname=bc3450\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"kernel_addr=fc0a0000\0" \
"ramdisk_addr=fc1c0000\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ideargs=setenv bootargs root=/dev/hda2 ro\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"addcons=setenv bootargs $(bootargs) " \
"console=ttyS0,$(baudrate) console=tty0\0" \
"flash_self=run ramargs addip addcons;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
"net_nfs=tftp 200000 $(bootfile); " \
"run nfsargs addip addcons; bootm\0" \
"ide_nfs=run nfsargs addip addcons; " \
"disk 200000 0:1; bootm\0" \
"ide_ide=run ideargs addip addcons; " \
"disk 200000 0:1; bootm\0" \
"usb_self=run usbload; run ramargs addip addcons; " \
"bootm 200000 400000\0" \
"usbload=usb reset; usb scan; usbboot 200000 0:1; " \
"usbboot 400000 0:2\0" \
"bootfile=uImage\0" \
"load=tftp 200000 $(u-boot)\0" \
"u-boot=u-boot.bin\0" \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 $(filesize);" \
"protect on FC000000 FC05FFFF\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
/*
* IPB Bus clocking configuration.
*/
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
/*
* I2C clock frequency
*
* Please notice, that the resulting clock frequency could differ from the
* configured value. This is because the I2C clock is derived from system
* clock over a frequency divider with only a few divider values. U-boot
* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
* approximation allways lies below the configured value, never above.
*/
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration for I²C EEPROM M24C32
* M24C64 should work also. For other EEPROMs config should be verified.
*
* The TQM5200 module may hold an EEPROM at address 0x50.
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
/*
* RTC configuration
*/
#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
# define CONFIG_RTC_M41T11 1
# define CONFIG_SYS_I2C_RTC_ADDR 0x68
#else
# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
# define CONFIG_BOARD_EARLY_INIT_R
#endif
/*
* Flash configuration
*/
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
/* use CFI flash driver if no module variant is spezified */
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
#else /* CONFIG_SYS_LOWBOOT */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
#endif /* CONFIG_SYS_LOWBOOT */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=TQM5200-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
"1408k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
"16m(big-fs)," \
"8m(misc)"
/*
* Environment settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/*
* Memory map
*/
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif /*CONFIG_POST*/
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*
* Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_MII100
#undef CONFIG_MPC5xxx_MII10
#define CONFIG_PHY_ADDR 0x00
/*
* GPIO configuration on BC3450
*
* PSC1: UART1 (Service-UART) [0x xxxxxxx4]
* PSC2: UART2 [0x xxxxxx4x]
* or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
* PSC3: USB2 [0x xxxxx1xx]
* USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
* (this has to match
* CONFIG_USB_CONFIG which is
* used by usb_ohci.c to set
* the USB ports)
* Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
* (this is reset to '5'
* in FEC driver: fec.c)
* PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
* ATA/CS: ??? [0x x1xxxxxx]
* FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
* CS1: Use Pin gpio_wkup_6 as second
* SDRAM chip select (mem_cs1)
* Timer: CAN2 / SPI
* I2C: CAN1 / I²C2 [0x bxxxxxxx]
*/
#ifdef CONFIG_BC3450_AC97
# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
#else /* PSC2=UART2 */
# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
/* more extensive mem test */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Enable loopw command.
*/
#define CONFIG_LOOPW
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
#endif
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
/* automatic configuration of chip selects */
#ifdef CONFIG_TQM5200
# define CONFIG_LAST_STAGE_INIT
#endif /* CONFIG_TQM5200 */
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
#ifdef CONFIG_TQM5200
# define CONFIG_SYS_CS2_START 0xE5000000
# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
# define CONFIG_SYS_CS2_CFG 0x0004D930
#endif /* CONFIG_TQM5200 */
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
#ifdef CONFIG_TQM5200
# define SM501_FB_BASE 0xE0000000
# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
# define CONFIG_SYS_CS1_CFG 0x8F48FF70
# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
#endif /* CONFIG_TQM5200 */
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
/* flash and SM501 */
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
/*
* USB stuff
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
/*
* IDE/ATA stuff Supports IDE harddisk
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
#endif /* __CONFIG_H */
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