Heiko Schocher
18 years ago
parent
ee58ea2689
commit
fa23044564
@ -0,0 +1,40 @@ |
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
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$(LIB): .depend $(OBJS) |
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$(AR) crv $@ $(OBJS)
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,34 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# TQM8272 boards
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#
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# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h
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# for the "final" configuration, with U-Boot in flash, or the address
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# in RAM where U-Boot is loaded at for debugging.
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#
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TEXT_BASE = 0x40000000
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,126 @@ |
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/* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(powerpc) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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cpu/mpc8260/start.o (.text) |
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*(.text) |
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common/environment.o(.text) |
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*(.fixup) |
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*(.got1) |
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. = ALIGN(16); |
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*(.rodata) |
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*(.rodata1) |
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*(.rodata.str1.4) |
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*(.eh_frame) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x0FFF) & 0xFFFFF000; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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*(.got) |
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_GOT2_TABLE_ = .; |
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*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
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.data : |
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{ |
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*(.data) |
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*(.data1) |
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*(.sdata) |
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*(.sdata2) |
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*(.dynamic) |
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CONSTRUCTORS |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(4096); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(4096); |
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__init_end = .; |
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__bss_start = .; |
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.bss : |
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{ |
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*(.sbss) *(.scommon) |
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*(.dynbss) |
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*(.bss) |
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*(COMMON) |
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} |
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_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -0,0 +1,758 @@ |
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/*
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* (C) Copyright 2006 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ |
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#define CONFIG_MPC8272_FAMILY 1 |
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#define CONFIG_TQM8272 1 |
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#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ |
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#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ |
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#define STK82xx_150 1 /* on a STK82xx.150 */ |
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#define CONFIG_CPM2 1 /* Has a CPM2 */ |
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#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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#define CONFIG_BOARD_EARLY_INIT_R 1 |
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#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) |
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#define CONFIG_BAUDRATE 230400 |
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#else |
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#define CONFIG_BAUDRATE 115200 |
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#endif |
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#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"netdev=eth0\0" \
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"consdev=ttyCPM0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"hostname=tqm8272\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addcons=setenv bootargs ${bootargs} " \
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"console=$(consdev),$(baudrate)\0" \
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"flash_nfs=run nfsargs addip addcons;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addcons;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 300000 ${bootfile};" \
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"run nfsargs addip addcons;bootm\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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"bootfile=/tftpboot/tqm8272/uImage\0" \
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"kernel_addr=40080000\0" \
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"ramdisk_addr=40100000\0" \
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"load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \
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"update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
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"cp.b 300000 40000000 40000;" \
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"setenv filesize;saveenv\0" \
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"cphwib=cp.b 4003fc00 33fc00 400\0" \
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"upd=run load;run cphwib;run update\0" \
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"" |
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#define CONFIG_BOOTCOMMAND "run flash_self" |
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#define CONFIG_I2C 1 |
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#if CONFIG_I2C |
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/* enable I2C and select the hardware/software driver */ |
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#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
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#define ADD_CMD_I2C CFG_CMD_I2C | \ |
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CFG_CMD_DATE |\
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CFG_CMD_DTT |\
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CFG_CMD_EEPROM |
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
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#define CFG_I2C_SLAVE 0x7F |
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/*
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* Software (bit-bang) I2C driver configuration |
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*/ |
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#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
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#define I2C_ACTIVE (iop->pdir |= 0x00010000) |
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#define I2C_TRISTATE (iop->pdir &= ~0x00010000) |
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#define I2C_READ ((iop->pdat & 0x00010000) != 0) |
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#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ |
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else iop->pdat &= ~0x00010000 |
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#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ |
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else iop->pdat &= ~0x00020000 |
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
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#define CONFIG_I2C_X |
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/* EEPROM */ |
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#define CFG_I2C_EEPROM_ADDR_LEN 2 |
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
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#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ |
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#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ |
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/* I2C RTC */ |
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#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ |
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#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
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/* I2C SYSMON (LM75) */ |
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ |
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#define CFG_DTT_MAX_TEMP 70 |
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#define CFG_DTT_LOW_TEMP -30 |
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#define CFG_DTT_HYSTERESIS 3 |
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#else |
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#undef CONFIG_HARD_I2C |
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#undef CONFIG_SOFT_I2C |
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#define ADD_CMD_I2C 0 |
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#endif |
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|
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/*
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* select serial console configuration |
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* |
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
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* for SCC). |
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* |
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* if CONFIG_CONS_NONE is defined, then the serial console routines must |
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* defined elsewhere (for example, on the cogent platform, there are serial |
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* ports on the motherboard which are used for the serial console - see |
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* cogent/cma101/serial.[ch]). |
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*/ |
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#define CONFIG_CONS_ON_SMC /* define if console on SMC */ |
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#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
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#undef CONFIG_CONS_NONE /* define if console on something else*/ |
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#ifdef CONFIG_82xx_CONS_SMC1 |
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#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
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#endif |
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#ifdef CONFIG_82xx_CONS_SMC2 |
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#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ |
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#endif |
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|
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#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ |
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#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ |
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#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ |
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|
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/*
|
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* select ethernet configuration |
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* |
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
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* for FCC) |
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* |
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
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* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
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* from CONFIG_COMMANDS to remove support for networking. |
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* |
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* (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the |
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* X.29 connector, and FCC2 is hardwired to the X.1 connector) |
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*/ |
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#define CFG_FCC_ETHERNET |
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|
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#if defined(CFG_FCC_ETHERNET) |
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#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
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#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
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#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
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#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ |
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#else |
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#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
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#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
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#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
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#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ |
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#endif |
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|
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#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) |
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|
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/*
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* - RX clk is CLK11 |
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* - TX clk is CLK12 |
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*/ |
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# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) |
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|
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#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) |
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|
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/*
|
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* - Rx-CLK is CLK13 |
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* - Tx-CLK is CLK14 |
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* - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
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* - Enable Full Duplex in FSMR |
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*/ |
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# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
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# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) |
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# define CFG_CPMFCR_RAMTYPE 0 |
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# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
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|
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#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ |
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|
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#define CONFIG_MII /* MII PHY management */ |
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#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
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/*
|
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* GPIO pins used for bit-banged MII communications |
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*/ |
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#define MDIO_PORT 2 /* Port C */ |
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|
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#if STK82xx_150 |
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#define CFG_MDIO_PIN 0x00008000 /* PC16 */ |
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#define CFG_MDC_PIN 0x00004000 /* PC17 */ |
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#endif |
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|
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#if STK82xx_100 |
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#define CFG_MDIO_PIN 0x00000002 /* PC30 */ |
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#define CFG_MDC_PIN 0x00000001 /* PC31 */ |
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#endif |
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|
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#if 1 |
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#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) |
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#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) |
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#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) |
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|
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#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ |
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else iop->pdat &= ~CFG_MDIO_PIN |
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|
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#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ |
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else iop->pdat &= ~CFG_MDC_PIN |
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#else |
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#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CFG_MDIO_PIN; iop->pdir = tmp;}) |
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#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;}) |
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#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) |
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|
||||
#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDIO_PIN; iop->pdat = tmp;}\ |
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else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;} |
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|
||||
#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDC_PIN; iop->pdat = tmp;}\ |
||||
else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;} |
||||
#endif |
||||
|
||||
#define MIIDELAY udelay(1) |
||||
|
||||
|
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_PING | \
|
||||
ADD_CMD_I2C | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_SNTP ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if 0 |
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
#endif |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x300000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_RESET_ADDRESS 0x40000104 /* "bad" address */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CAN stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_CAN_BASE 0x51000000 |
||||
#define CFG_CAN_SIZE 1 |
||||
#define CFG_CAN_BR ((CFG_CAN_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_UPMC |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_CAN_OR (MEG_TO_AM(CFG_CAN_SIZE) |\ |
||||
ORxU_BI) |
||||
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk |
||||
* The main FLASH is whichever is connected to *CS0. |
||||
*/ |
||||
#define CFG_FLASH0_BASE 0x40000000 |
||||
#define CFG_FLASH0_SIZE 32 /* 32 MB */ |
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/ |
||||
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_FLASH_CFI /* flash is CFI compat. */ |
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ |
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ |
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
#define CFG_UPDATE_FLASH_SIZE |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) |
||||
#define CFG_ENV_SIZE 0x20000 |
||||
#define CFG_ENV_SECT_SIZE 0x20000 |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND 0x20000 |
||||
|
||||
/* Where is the Hardwareinformation Block (from Monitor Sources) */ |
||||
#define MON_RES_LENGTH (0x0003FC00) |
||||
#define HWIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH) |
||||
#define HWIB_INFO_LEN 512 |
||||
#define CIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) |
||||
#define CIB_INFO_LEN 512 |
||||
|
||||
#define CFG_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ |
||||
#define CFG_HWINFO_SIZE 0x00000060 /* size of HW Info block */ |
||||
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND-FLASH stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
||||
|
||||
#define CFG_NAND_CS_DIST 0x80 |
||||
#define CFG_NAND_UPM_WRITE_CMD_OFS 0x20 |
||||
#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x40 |
||||
|
||||
#define CFG_NAND_BR ((CFG_NAND0_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_UPMB |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_NAND_OR (MEG_TO_AM(CFG_NAND_SIZE) |\ |
||||
ORxU_BI |\
|
||||
ORxU_EHTR_8IDLE) |
||||
|
||||
#define CFG_NAND_SIZE 1 |
||||
#define CFG_NAND0_BASE 0x50000000 |
||||
#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) |
||||
#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) |
||||
#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) |
||||
|
||||
#define CFG_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ |
||||
CFG_NAND1_BASE, \
|
||||
CFG_NAND2_BASE, \
|
||||
CFG_NAND3_BASE, \
|
||||
} |
||||
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) |
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) |
||||
#define WRITE_NAND_UPM(d, adr, off) do \ |
||||
{ \
|
||||
volatile unsigned char *addr = (unsigned char *) (adr + off); \
|
||||
WRITE_NAND(d, addr); \
|
||||
} while(0) |
||||
|
||||
#endif /* CFG_CMD_NAND */ |
||||
|
||||
#define CONFIG_PCI |
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
||||
#define CONFIG_PCI_PNP |
||||
#define CONFIG_EEPRO100 |
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
||||
#define CONFIG_PCI_SCAN_SHOW |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CFG_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
||||
*/ |
||||
#if 0 |
||||
#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) |
||||
|
||||
# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) |
||||
#else |
||||
#define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) |
||||
#endif |
||||
|
||||
/* no slaves so just fill with zeros */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE CFG_FLASH0_BASE |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
||||
HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CFG_RMR RMR_CSRE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ |
||||
#define BCR_APD01 0x10000000 |
||||
#define CFG_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#if defined(CONFIG_BOARD_GET_CPU_CLK_F) |
||||
#define CFG_SIUMCR_LOW (SIUMCR_DPPC00) |
||||
#define CFG_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) |
||||
#else |
||||
#define CFG_SIUMCR (SIUMCR_DPPC00) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
*----------------------------------------------------------------------- |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
* Ensure DFBRG is Divide by 16 |
||||
*/ |
||||
#define CFG_SCCR SCCR_DFBRG01 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Device |
||||
* ---- --- ------- ------ ------ |
||||
* 0 60x GPCM 32 bit FLASH |
||||
* 1 60x SDRAM 64 bit SDRAM |
||||
* 2 60x UPMB 8 bit NAND |
||||
* 3 60x UPMC 8 bit CAN
|
||||
* |
||||
*/ |
||||
|
||||
/* Initialize SDRAM
|
||||
*/ |
||||
#undef CFG_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ |
||||
|
||||
#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ |
||||
|
||||
/* Minimum mask to separate preliminary
|
||||
* address ranges for CS[0:2] |
||||
*/ |
||||
#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ |
||||
|
||||
#define CFG_MPTPR 0x4000 |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Address for Mode Register Set (MRS) command |
||||
*----------------------------------------------------------------------------- |
||||
* In fact, the address is rather configuration data presented to the SDRAM on |
||||
* its address lines. Because the address lines may be mux'ed externally either |
||||
* for 8 column or 9 column devices, some bits appear twice in the 8260's |
||||
* address: |
||||
* |
||||
* | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | |
||||
* | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | |
||||
* 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | |
||||
* 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | |
||||
* Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | |
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_MRS_OFFS 0x00000110 |
||||
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*/ |
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_32 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV4 |\
|
||||
ORxG_SCY_8_CLK |\
|
||||
ORxG_TRLX) |
||||
|
||||
/* SDRAM on TQM8272 can have either 8 or 9 columns.
|
||||
* The number affects configuration values. |
||||
*/ |
||||
|
||||
/* Bank 1 - 60x bus SDRAM
|
||||
*/ |
||||
#define CFG_PSRT 0x20 /* Low Value */ |
||||
/* #define CFG_PSRT 0x10 Fast Value */ |
||||
#define CFG_LSRT 0x20 /* Local Bus */ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR1_PRELIM CFG_OR1_8COL |
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/ |
||||
#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A7 |\
|
||||
ORxS_NUMR_12) |
||||
|
||||
#define CFG_PSDMR_8COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A15_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A8 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_BUFCMD |\
|
||||
PSDMR_CL_2) |
||||
|
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/ |
||||
#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A5 |\
|
||||
ORxS_NUMR_13) |
||||
|
||||
#define CFG_PSDMR_9COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A16_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A7 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_BUFCMD |\
|
||||
PSDMR_CL_2) |
||||
|
||||
#define CFG_OR1_10COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A4 |\
|
||||
ORxS_NUMR_13) |
||||
|
||||
#define CFG_PSDMR_10COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A17_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A4 |\
|
||||
PSDMR_RFRC_6_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
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PSDMR_BUFCMD |\
|
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PSDMR_CL_2) |
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|
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#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ |
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#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ |
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#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ |
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#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ |
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#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ |
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#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ |
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|
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#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ |
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#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ |
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#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ |
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#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ |
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#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ |
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#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ |
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|
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#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ |
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#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ |
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#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ |
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#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ |
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#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ |
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#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ |
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|
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#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ |
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#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ |
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#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ |
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#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ |
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#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ |
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#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ |
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|
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
#endif /* __CONFIG_H */ |
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Reference in new issue