RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from coreboot, support 4GB lpddr3 in this version. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Added rockchip: tag: Signed-off-by: Simon Glass <sjg@chromium.org>master
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/*
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* Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_SDRAM_RK3399_H |
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#define _ASM_ARCH_SDRAM_RK3399_H |
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enum { |
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DDR3 = 0x3, |
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LPDDR2 = 0x5, |
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LPDDR3 = 0x6, |
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LPDDR4 = 0x7, |
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UNUSED = 0xFF |
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}; |
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struct rk3399_ddr_pctl_regs { |
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u32 denali_ctl[332]; |
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}; |
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struct rk3399_ddr_publ_regs { |
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u32 denali_phy[959]; |
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}; |
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struct rk3399_ddr_pi_regs { |
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u32 denali_pi[200]; |
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}; |
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struct rk3399_msch_regs { |
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u32 coreid; |
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u32 revisionid; |
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u32 ddrconf; |
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u32 ddrsize; |
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u32 ddrtiminga0; |
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u32 ddrtimingb0; |
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u32 ddrtimingc0; |
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u32 devtodev0; |
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u32 reserved0[(0x110 - 0x20) / 4]; |
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u32 ddrmode; |
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u32 reserved1[(0x1000 - 0x114) / 4]; |
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u32 agingx0; |
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}; |
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struct rk3399_msch_timings { |
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u32 ddrtiminga0; |
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u32 ddrtimingb0; |
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u32 ddrtimingc0; |
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u32 devtodev0; |
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u32 ddrmode; |
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u32 agingx0; |
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}; |
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struct rk3399_ddr_cic_regs { |
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u32 cic_ctrl0; |
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u32 cic_ctrl1; |
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u32 cic_idle_th; |
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u32 cic_cg_wait_th; |
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u32 cic_status0; |
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u32 cic_status1; |
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u32 cic_ctrl2; |
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u32 cic_ctrl3; |
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u32 cic_ctrl4; |
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}; |
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/* DENALI_CTL_00 */ |
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#define START 1 |
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/* DENALI_CTL_68 */ |
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#define PWRUP_SREFRESH_EXIT (1 << 16) |
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/* DENALI_CTL_274 */ |
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#define MEM_RST_VALID 1 |
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struct rk3399_sdram_channel { |
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unsigned int rank; |
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/* dram column number, 0 means this channel is invalid */ |
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unsigned int col; |
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/* dram bank number, 3:8bank, 2:4bank */ |
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unsigned int bk; |
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/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ |
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unsigned int bw; |
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/* die buswidth, 2:32bit, 1:16bit, 0:8bit */ |
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unsigned int dbw; |
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/*
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* row_3_4 = 1: 6Gb or 12Gb die |
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* row_3_4 = 0: normal die, power of 2 |
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*/ |
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unsigned int row_3_4; |
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unsigned int cs0_row; |
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unsigned int cs1_row; |
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unsigned int ddrconfig; |
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struct rk3399_msch_timings noc_timings; |
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}; |
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struct rk3399_base_params { |
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unsigned int ddr_freq; |
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unsigned int dramtype; |
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unsigned int num_channels; |
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unsigned int stride; |
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unsigned int odt; |
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}; |
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struct rk3399_sdram_params { |
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struct rk3399_sdram_channel ch[2]; |
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struct rk3399_base_params base; |
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struct rk3399_ddr_pctl_regs pctl_regs; |
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struct rk3399_ddr_pi_regs pi_regs; |
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struct rk3399_ddr_publ_regs phy_regs; |
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}; |
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#define PI_CA_TRAINING (1 << 0) |
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#define PI_WRITE_LEVELING (1 << 1) |
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#define PI_READ_GATE_TRAINING (1 << 2) |
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#define PI_READ_LEVELING (1 << 3) |
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#define PI_WDQ_LEVELING (1 << 4) |
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#define PI_FULL_TRAINING 0xff |
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#endif |
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Rockchip Dynamic Memory Controller Driver |
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Required properties: |
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- compatible: "rockchip,rk3399-dmc", "syscon" |
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- rockchip,cru: this driver should access cru regs, so need get cru here |
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- rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here |
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- rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here |
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- rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here |
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- rockchip,cic: this driver should access cic regs, so need get cic here |
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- reg: dynamic ram protocol controller(PCTL) address, PHY Independent(PI) address, phy controller(PHYCTL) address and memory schedule(MSCH) address |
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- clock: must include clock specifiers corresponding to entries in the clock-names property. |
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Must contain |
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dmc_clk: for ddr working frequency |
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- rockchip,sdram-params: SDRAM parameters, including all the information by ddr driver: |
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Must contain |
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Genarate by vendor tool and adjust for U-Boot dtsi. |
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Example: |
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dmc: dmc { |
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u-boot,dm-pre-reloc; |
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compatible = "rockchip,rk3399-dmc"; |
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devfreq-events = <&dfi>; |
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; |
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clocks = <&cru SCLK_DDRCLK>; |
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clock-names = "dmc_clk"; |
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reg = <0x0 0xffa80000 0x0 0x0800 |
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0x0 0xffa80800 0x0 0x1800 |
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0x0 0xffa82000 0x0 0x2000 |
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0x0 0xffa84000 0x0 0x1000 |
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0x0 0xffa88000 0x0 0x0800 |
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0x0 0xffa88800 0x0 0x1800 |
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0x0 0xffa8a000 0x0 0x2000 |
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0x0 0xffa8c000 0x0 0x1000>; |
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}; |
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&dmc { |
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rockchip,sdram-params = < |
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0x2 |
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0xa |
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0x3 |
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... |
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>; |
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}; |
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