The patch add header files to support the Freescale i.MX51 processor, setting definitions for internal registers. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fred Fan <fanyefeng@gmail.com>master
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/*
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* needed for cpu/arm_cortexa8/mx51/lowlevel_init.S |
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* |
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* These should be auto-generated |
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*/ |
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/* CCM */ |
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#define CLKCTL_CCR 0x00 |
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#define CLKCTL_CCDR 0x04 |
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#define CLKCTL_CSR 0x08 |
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#define CLKCTL_CCSR 0x0C |
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#define CLKCTL_CACRR 0x10 |
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#define CLKCTL_CBCDR 0x14 |
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#define CLKCTL_CBCMR 0x18 |
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#define CLKCTL_CSCMR1 0x1C |
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#define CLKCTL_CSCMR2 0x20 |
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#define CLKCTL_CSCDR1 0x24 |
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#define CLKCTL_CS1CDR 0x28 |
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#define CLKCTL_CS2CDR 0x2C |
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#define CLKCTL_CDCDR 0x30 |
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#define CLKCTL_CHSCCDR 0x34 |
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#define CLKCTL_CSCDR2 0x38 |
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#define CLKCTL_CSCDR3 0x3C |
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#define CLKCTL_CSCDR4 0x40 |
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#define CLKCTL_CWDR 0x44 |
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#define CLKCTL_CDHIPR 0x48 |
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#define CLKCTL_CDCR 0x4C |
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#define CLKCTL_CTOR 0x50 |
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#define CLKCTL_CLPCR 0x54 |
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#define CLKCTL_CISR 0x58 |
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#define CLKCTL_CIMR 0x5C |
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#define CLKCTL_CCOSR 0x60 |
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#define CLKCTL_CGPR 0x64 |
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#define CLKCTL_CCGR0 0x68 |
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#define CLKCTL_CCGR1 0x6C |
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#define CLKCTL_CCGR2 0x70 |
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#define CLKCTL_CCGR3 0x74 |
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#define CLKCTL_CCGR4 0x78 |
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#define CLKCTL_CCGR5 0x7C |
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#define CLKCTL_CCGR6 0x80 |
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#define CLKCTL_CMEOR 0x84 |
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/* DPLL */ |
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#define PLL_DP_CTL 0x00 |
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#define PLL_DP_CONFIG 0x04 |
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#define PLL_DP_OP 0x08 |
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#define PLL_DP_MFD 0x0C |
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#define PLL_DP_MFN 0x10 |
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#define PLL_DP_HFS_OP 0x1C |
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#define PLL_DP_HFS_MFD 0x20 |
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#define PLL_DP_HFS_MFN 0x24 |
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/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ |
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#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ |
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#define MXC_CCM_BASE CCM_BASE_ADDR |
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/* DPLL register mapping structure */ |
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struct mxc_pll_reg { |
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u32 ctrl; |
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u32 config; |
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u32 op; |
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u32 mfd; |
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u32 mfn; |
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u32 mfn_minus; |
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u32 mfn_plus; |
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u32 hfs_op; |
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u32 hfs_mfd; |
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u32 hfs_mfn; |
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u32 mfn_togc; |
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u32 destat; |
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}; |
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/* Register maping of CCM*/ |
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struct mxc_ccm_reg { |
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u32 ccr; /* 0x0000 */ |
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u32 ccdr; |
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u32 csr; |
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u32 ccsr; |
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u32 cacrr; /* 0x0010*/ |
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u32 cbcdr; |
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u32 cbcmr; |
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u32 cscmr1; |
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u32 cscmr2; /* 0x0020 */ |
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u32 cscdr1; |
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u32 cs1cdr; |
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u32 cs2cdr; |
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u32 cdcdr; /* 0x0030 */ |
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u32 chscdr; |
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u32 cscdr2; |
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u32 cscdr3; |
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u32 cscdr4; /* 0x0040 */ |
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u32 cwdr; |
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u32 cdhipr; |
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u32 cdcr; |
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u32 ctor; /* 0x0050 */ |
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u32 clpcr; |
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u32 cisr; |
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u32 cimr; |
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u32 ccosr; /* 0x0060 */ |
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u32 cgpr; |
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u32 CCGR0; |
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u32 CCGR1; |
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u32 CCGR2; /* 0x0070 */ |
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u32 CCGR3; |
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u32 CCGR4; |
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u32 CCGR5; |
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u32 CCGR6; /* 0x0080 */ |
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u32 cmeor; |
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}; |
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/* Define the bits in register CACRR */ |
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#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 |
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#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 |
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/* Define the bits in register CBCDR */ |
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#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) |
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#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) |
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#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 |
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#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) |
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#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 |
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#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) |
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#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 |
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#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) |
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#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 |
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#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) |
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#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 |
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#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) |
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#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 |
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#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) |
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#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 |
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#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) |
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#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 |
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#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) |
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#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 |
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#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 |
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/* Define the bits in register CSCMR1 */ |
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#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 |
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#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) |
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#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 |
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#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) |
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#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26 |
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#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) |
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#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 |
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#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) |
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#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 |
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#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) |
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#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 |
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#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) |
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#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) |
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#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) |
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 |
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) |
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 |
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) |
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 |
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) |
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#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) |
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#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) |
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#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 |
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#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) |
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#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) |
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#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) |
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#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 |
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#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) |
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#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 |
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#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) |
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#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) |
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#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 |
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/* Define the bits in register CSCDR2 */ |
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#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 |
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#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) |
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#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 |
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#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) |
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#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 |
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#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) |
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#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 |
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#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) |
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#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 |
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#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) |
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#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0 |
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#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F |
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/* Define the bits in register CBCMR */ |
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#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 |
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#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) |
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#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 |
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#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) |
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#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 |
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#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) |
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#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 |
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#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) |
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#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 |
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#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) |
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#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 |
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#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) |
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#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) |
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#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) |
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/* Define the bits in register CSCDR1 */ |
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 |
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) |
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 |
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) |
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 |
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) |
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#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 |
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#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) |
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 |
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) |
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 |
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) |
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 |
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) |
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#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 |
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#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) |
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#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 |
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#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 |
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#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ |
@ -0,0 +1,282 @@ |
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/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __ASM_ARCH_MXC_MX51_H__ |
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#define __ASM_ARCH_MXC_MX51_H__ |
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#define __REG(x) (*((volatile u32 *)(x))) |
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#define __REG16(x) (*((volatile u16 *)(x))) |
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#define __REG8(x) (*((volatile u8 *)(x))) |
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/*
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* IRAM |
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*/ |
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#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ |
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/*
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* Graphics Memory of GPU |
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*/ |
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#define GPU_BASE_ADDR 0x20000000 |
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#define GPU_CTRL_BASE_ADDR 0x30000000 |
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#define IPU_CTRL_BASE_ADDR 0x40000000 |
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/*
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* Debug |
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*/ |
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#define DEBUG_BASE_ADDR 0x60000000 |
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#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) |
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#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) |
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#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) |
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#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) |
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#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) |
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#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) |
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#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) |
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#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) |
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/*
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* SPBA global module enabled #0 |
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*/ |
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#define SPBA0_BASE_ADDR 0x70000000 |
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#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) |
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#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) |
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#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) |
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#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) |
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#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) |
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#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) |
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#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) |
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#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) |
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#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) |
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#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) |
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#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) |
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#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) |
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/*
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* AIPS 1 |
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*/ |
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#define AIPS1_BASE_ADDR 0x73F00000 |
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#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) |
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#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) |
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#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) |
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#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) |
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#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) |
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#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) |
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#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) |
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#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) |
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#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) |
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#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) |
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#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) |
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#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) |
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#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) |
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#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) |
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#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) |
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#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) |
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#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) |
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#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) |
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#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) |
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#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) |
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/*
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* AIPS 2 |
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*/ |
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#define AIPS2_BASE_ADDR 0x83F00000 |
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#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) |
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#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) |
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#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) |
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#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) |
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#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) |
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#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) |
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#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) |
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#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) |
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#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) |
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#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) |
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#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) |
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#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) |
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#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) |
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#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) |
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#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) |
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#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) |
||||
#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) |
||||
#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) |
||||
#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) |
||||
#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) |
||||
#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) |
||||
#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) |
||||
#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) |
||||
#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) |
||||
#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) |
||||
#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) |
||||
#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) |
||||
#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) |
||||
#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) |
||||
#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) |
||||
#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) |
||||
#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) |
||||
|
||||
#define TZIC_BASE_ADDR 0x8FFFC000 |
||||
|
||||
/*
|
||||
* Memory regions and CS |
||||
*/ |
||||
#define CSD0_BASE_ADDR 0x90000000 |
||||
#define CSD1_BASE_ADDR 0xA0000000 |
||||
#define CS0_BASE_ADDR 0xB0000000 |
||||
#define CS1_BASE_ADDR 0xB8000000 |
||||
#define CS2_BASE_ADDR 0xC0000000 |
||||
#define CS3_BASE_ADDR 0xC8000000 |
||||
#define CS4_BASE_ADDR 0xCC000000 |
||||
#define CS5_BASE_ADDR 0xCE000000 |
||||
|
||||
/*
|
||||
* NFC |
||||
*/ |
||||
#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ |
||||
|
||||
/*!
|
||||
* Number of GPIO port as defined in the IC Spec |
||||
*/ |
||||
#define GPIO_PORT_NUM 4 |
||||
/*!
|
||||
* Number of GPIO pins per port |
||||
*/ |
||||
#define GPIO_NUM_PIN 32 |
||||
|
||||
#define IIM_SREV 0x24 |
||||
#define ROM_SI_REV 0x48 |
||||
|
||||
#define NFC_BUF_SIZE 0x1000 |
||||
|
||||
/* M4IF */ |
||||
#define M4IF_FBPM0 0x40 |
||||
#define M4IF_FIDBP 0x48 |
||||
|
||||
/* Assuming 24MHz input clock with doubler ON */ |
||||
/* MFI PDF */ |
||||
#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) |
||||
#define DP_MFD_850 (48 - 1) |
||||
#define DP_MFN_850 41 |
||||
|
||||
#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) |
||||
#define DP_MFD_800 (3 - 1) |
||||
#define DP_MFN_800 1 |
||||
|
||||
#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) |
||||
#define DP_MFD_700 (24 - 1) |
||||
#define DP_MFN_700 7 |
||||
|
||||
#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) |
||||
#define DP_MFD_665 (96 - 1) |
||||
#define DP_MFN_665 89 |
||||
|
||||
#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) |
||||
#define DP_MFD_532 (24 - 1) |
||||
#define DP_MFN_532 13 |
||||
|
||||
#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) |
||||
#define DP_MFD_400 (3 - 1) |
||||
#define DP_MFN_400 1 |
||||
|
||||
#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) |
||||
#define DP_MFD_216 (4 - 1) |
||||
#define DP_MFN_216 3 |
||||
|
||||
#define CHIP_REV_1_0 0x10 |
||||
#define CHIP_REV_1_1 0x11 |
||||
#define CHIP_REV_2_0 0x20 |
||||
#define CHIP_REV_2_5 0x25 |
||||
#define CHIP_REV_3_0 0x30 |
||||
|
||||
#define BOARD_REV_1_0 0x0 |
||||
#define BOARD_REV_2_0 0x1 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
enum mxc_clock { |
||||
MXC_ARM_CLK = 0, |
||||
MXC_AHB_CLK, |
||||
MXC_IPG_CLK, |
||||
MXC_IPG_PERCLK, |
||||
MXC_UART_CLK, |
||||
MXC_CSPI_CLK, |
||||
MXC_FEC_CLK, |
||||
}; |
||||
|
||||
struct clkctl { |
||||
u32 ccr; |
||||
u32 ccdr; |
||||
u32 csr; |
||||
u32 ccsr; |
||||
u32 cacrr; |
||||
u32 cbcdr; |
||||
u32 cbcmr; |
||||
u32 cscmr1; |
||||
u32 cscmr2; |
||||
u32 cscdr1; |
||||
u32 cs1cdr; |
||||
u32 cs2cdr; |
||||
u32 cdcdr; |
||||
u32 chsccdr; |
||||
u32 cscdr2; |
||||
u32 cscdr3; |
||||
u32 cscdr4; |
||||
u32 cwdr; |
||||
u32 cdhipr; |
||||
u32 cdcr; |
||||
u32 ctor; |
||||
u32 clpcr; |
||||
u32 cisr; |
||||
u32 cimr; |
||||
u32 ccosr; |
||||
u32 cgpr; |
||||
u32 ccgr0; |
||||
u32 ccgr1; |
||||
u32 ccgr2; |
||||
u32 ccgr3; |
||||
u32 ccgr4; |
||||
u32 ccgr5; |
||||
u32 ccgr6; |
||||
u32 cmeor; |
||||
}; |
||||
|
||||
/* WEIM registers */ |
||||
struct weim { |
||||
u32 csgcr1; |
||||
u32 csgcr2; |
||||
u32 csrcr1; |
||||
u32 csrcr2; |
||||
u32 cswcr1; |
||||
u32 cswcr2; |
||||
}; |
||||
|
||||
/*!
|
||||
* NFMS bit in RCSR register for pagesize of nandflash |
||||
*/ |
||||
#define NFMS (*((volatile u32 *)(CCM_BASE_ADDR+0x18))) |
||||
#define NFMS_BIT 8 |
||||
#define NFMS_NF_DWIDTH 14 |
||||
#define NFMS_NF_PG_SZ 8 |
||||
|
||||
extern unsigned int get_board_rev(void); |
||||
extern int is_soc_rev(int rev); |
||||
|
||||
#endif /* __ASSEMBLER__*/ |
||||
|
||||
#endif /* __ASM_ARCH_MXC_MX51_H__ */ |
Loading…
Reference in new issue