mx6: Support SKS-Kinkel sksimx6 Board

Board has 1GB RAM and boots from SD Card U-Boot SPL 2018.01-rc3-00005-ga1898b8 (Jan 02 2018 - 13:48:54) BT_FUSE_SEL already fused, will do nothing Trying to boot from MMC1 U-Boot 2018.01-rc3-00005-ga1898b8 (Jan 02 2018 - 13:48:54 +0100) CPU: Freescale i.MX6DL rev1.2 996 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 40C Reset cause: POR I2C: ready DRAM: 1 GiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC [PRIME] Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
7 years ago · fb8cac9366
parent 373b900341
commit fb8cac9366
7 changed files with 599 additions and 0 deletions
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@ -377,6 +377,10 @@ config TARGET_PFLA02
 config TARGET_SECOMX6
 	bool "secomx6 boards"

+config TARGET_SKSIMX6
+	bool "sks-imx6"
+	select SUPPORT_SPL
+
 config TARGET_TBS2910
 	bool "TBS2910 Matrix ARM mini PC"

@ -482,6 +486,7 @@ source "board/liebherr/display5/Kconfig"
 source "board/liebherr/mccmon6/Kconfig"
 source "board/logicpd/imx6/Kconfig"
 source "board/seco/Kconfig"
+source "board/sks-kinkel/sksimx6/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
--- a/board/sks-kinkel/sksimx6/Kconfig
+++ b/board/sks-kinkel/sksimx6/Kconfig
@ -0,0 +1,11 @@
+if TARGET_SKSIMX6
+
+config SYS_BOARD
+	default "sksimx6"
+
+config SYS_VENDOR
+	default "sks-kinkel"
+
+config SYS_CONFIG_NAME
+	default "sksimx6"
+endif
--- a/board/sks-kinkel/sksimx6/MAINTAINERS
+++ b/board/sks-kinkel/sksimx6/MAINTAINERS
@ -0,0 +1,6 @@
+SKS-Kinkel sksimx6
+M:	Stefano Babic <sbabic@denx.de>
+S:	Maintained
+F:	board/sks-kinkel/sksimx6/
+F:	include/configs/sksimx6.h
+F:	configs/sksimx6_defconfig
--- a/board/sks-kinkel/sksimx6/Makefile
+++ b/board/sks-kinkel/sksimx6/Makefile
@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+obj-y  := sksimx6.o
--- a/board/sks-kinkel/sksimx6/sksimx6.c
+++ b/board/sks-kinkel/sksimx6/sksimx6.c
@ -0,0 +1,426 @@
+/*
+ * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <micrel.h>
+
+#include <common.h>
+#include <malloc.h>
+#include <fuse.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const gpios_pads[] = {
+	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+iomux_v3_cfg_t const enet_pads1[] = {
+	/* pin 35 - 1 (PHY_AD2) on reset */
+	IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* pin 32 - 1 - (MODE0) all */
+	IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* pin 31 - 1 - (MODE1) all */
+	IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* pin 28 - 1 - (MODE2) all */
+	IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* pin 27 - 1 - (MODE3) all */
+	IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+	IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* pin 42 PHY nRST */
+	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+
+	/* min rx data delay */
+	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+				   0x0);
+	/* min tx data delay */
+	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+				   0x0);
+	/* max rx/tx clock delay, min rx/tx control */
+	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+				   0xf0f0);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#define ENET_NRST IMX_GPIO_NR(1, 25)
+
+void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+
+}
+
+int board_eth_init(bd_t *bis)
+{
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+	int ret;
+
+	setup_iomux_enet();
+
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return -EINVAL;
+	/* scan phy */
+	phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
+					PHY_INTERFACE_MODE_RGMII);
+
+	if (!phydev) {
+		ret = -EINVAL;
+		goto free_bus;
+	}
+	ret  = fec_probe(bis, -1, base, bus, phydev);
+	if (ret)
+		goto free_phydev;
+
+	return 0;
+
+free_phydev:
+	free(phydev);
+free_bus:
+	free(bus);
+	return ret;
+}
+
+int board_early_init_f(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Take in reset the ATMega processor */
+	SETUP_IOMUX_PADS(gpios_pads);
+	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC2_BASE_ADDR, 0},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 0)
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+		ret = 1;
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	SETUP_IOMUX_PADS(usdhc2_pads);
+	gpio_direction_input(USDHC2_CD_GPIO);
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	usdhc_cfg[0].max_bus_width = 4;
+
+	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	if (ret) {
+		printf("Warning: failed to initialize mmc dev \n");
+		return ret;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+
+/*
+ * Driving strength:
+ *   0x30 == 40 Ohm
+ *   0x28 == 48 Ohm
+ */
+#define IMX6SDL_DRIVE_STRENGTH	0x230
+
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+	/* quad = 1066, duallite = 800 */
+	.mem_speed = 1066,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0043004E,
+	.p0_mpwldectrl1 = 0x003D003F,
+	.p1_mpwldectrl0 = 0x00230021,
+	.p1_mpwldectrl1 = 0x0028003E,
+	.p0_mpdgctrl0 = 0x42580250,
+	.p0_mpdgctrl1 = 0x0238023C,
+	.p1_mpdgctrl0 = 0x422C0238,
+	.p1_mpdgctrl1 = 0x02180228,
+	.p0_mprddlctl = 0x44464A46,
+	.p1_mprddlctl = 0x44464A42,
+	.p0_mpwrdlctl = 0x36343236,
+	.p1_mpwrdlctl = 0x36343230,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_qdl = {
+	.dsize = 2,
+	.cs1_mirror = 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density = 32,
+	.ncs = 1,
+	.bi_on = 1,
+	.rtt_nom = 1,
+	.rtt_wr = 1,
+	.ralat = 5,
+	.walat = 0,
+	.mif3_mode = 3,
+	.rst_to_cke = 0x23,
+	.sde_to_rst = 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* set the default clock gate to save power */
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_cpu_type(MXC_CPU_MX6DL)) {
+		mt41k128m16jt_125.mem_speed = 800;
+		mem_qdl.rtt_nom = 1;
+		mem_qdl.rtt_wr = 1;
+
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
+	} else {
+		printf("Wrong CPU for this board\n");
+		return;
+	}
+
+	udelay(100);
+
+#ifdef CONFIG_MX6_DDRCAL
+
+	/* Perform DDR DRAM calibration */
+	mmdc_do_write_level_calibration(&mem_qdl);
+	mmdc_do_dqs_calibration(&mem_qdl);
+#endif
+}
+
+static void check_bootcfg(void)
+{
+	u32 val5, val6;
+
+	fuse_sense(0, 5, &val5);
+	fuse_sense(0, 6, &val6);
+	/* Check if boot from MMC */
+	if (val6 & 0x10) {
+		puts("BT_FUSE_SEL already fused, will do nothing\n");
+		return;
+	}
+	fuse_prog(0, 5, 0x00000840);
+	/* BT_FUSE_SEL */
+	fuse_prog(0, 6, 0x00000010);
+
+	do_reset(NULL, 0, 0, NULL);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Set fuses for new boards and reboot if not set */
+	check_bootcfg();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
--- a/configs/sksimx6_defconfig
+++ b/configs/sksimx6_defconfig
@ -0,0 +1,47 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_SKSIMX6=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_BOOTDELAY=1
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SILENT_U_BOOT_ONLY=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
--- a/include/configs/sksimx6.h
+++ b/include/configs/sksimx6.h
@ -0,0 +1,101 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __SKSIMX6_CONFIG_H
+#define __SKSIMX6_CONFIG_H
+
+#include <config_distro_defaults.h>
+
+#include "mx6_common.h"
+#include "imx6_spl.h"
+
+/* Thermal */
+#define CONFIG_IMX_THERMAL
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART1_BASE
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
+
+/* Ethernet */
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0x01
+
+#define CONFIG_MII
+#define CONFIG_PHY_MICREL_KSZ9021
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* Filesystem support */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE                (16 * 1024)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console},${baudrate}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+		"${netmask}:${hostname}:${netdev}:off\0"		\
+	"addmisc=setenv bootargs ${bootargs} ${miscargs}\0" 		\
+	"bootcmd=run mmcboot\0"						\
+	"bootfile=uImage\0"						\
+	"bootimage=uImage\0"						\
+	"console=ttymxc0\0"						\
+	"fdt_addr_r=0x18000000\0" 					\
+	"fdt_file=imx6dl-sks-cts.dtb\0"					\
+	"fdt_high=0xffffffff\0" 					\
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" 		\
+	"miscargs=quiet\0"						\
+	"mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0"		\
+	"mmcboot=if run mmcload;then " 					\
+		"run mmcargs addcons addmisc;"				\
+			"bootm;fi\0" 					\
+	"mmcload=mmc rescan;"						\
+		"load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
+	"mmcpart=1\0"							\
+	"mmcroot=/dev/mmcblk0p1\0"					\
+	"net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};"	\
+		"tftp ${fdt_addr_r} ${board_name}/${fdt_file};"		\
+		"run nfsargs addip addcons addmisc;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"nfsargs=setenv bootargs root=/dev/nfs "			\
+		"nfsroot=${serverip}:${nfsroot},v3 panic=1\0"
+
+#endif