Add driver for the RPC block in SPI-flash mode. This driver allows access to a SPI NOR flash attached to the RPC block and does not support RPC in Hyperflash mode. Note that this block is extremely selective when communicating with the SPI NOR. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master^2
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a405a55ba8
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/*
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* Renesas RCar Gen3 RPC QSPI driver |
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* |
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <clk.h> |
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#include <dm.h> |
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#include <dm/of_access.h> |
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#include <dt-structs.h> |
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#include <errno.h> |
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#include <linux/errno.h> |
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#include <spi.h> |
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#include <wait_bit.h> |
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#define RPC_CMNCR 0x0000 /* R/W */ |
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#define RPC_CMNCR_MD BIT(31) |
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#define RPC_CMNCR_SFDE BIT(24) |
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#define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) |
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#define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) |
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#define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) |
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#define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) |
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#define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \ |
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RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3)) |
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#define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14) |
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#define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12) |
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#define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8) |
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#define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \ |
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RPC_CMNCR_IO3FV(3)) |
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#define RPC_CMNCR_CPHAT BIT(6) |
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#define RPC_CMNCR_CPHAR BIT(5) |
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#define RPC_CMNCR_SSLP BIT(4) |
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#define RPC_CMNCR_CPOL BIT(3) |
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#define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0) |
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#define RPC_SSLDR 0x0004 /* R/W */ |
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#define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16) |
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#define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8) |
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#define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0) |
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#define RPC_DRCR 0x000C /* R/W */ |
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#define RPC_DRCR_SSLN BIT(24) |
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#define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16) |
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#define RPC_DRCR_RCF BIT(9) |
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#define RPC_DRCR_RBE BIT(8) |
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#define RPC_DRCR_SSLE BIT(0) |
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#define RPC_DRCMR 0x0010 /* R/W */ |
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#define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16) |
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#define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0) |
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#define RPC_DREAR 0x0014 /* R/W */ |
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#define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16) |
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#define RPC_DREAR_EAC(v) (((v) & 0x7) << 0) |
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#define RPC_DROPR 0x0018 /* R/W */ |
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#define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24) |
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#define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16) |
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#define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8) |
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#define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0) |
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#define RPC_DRENR 0x001C /* R/W */ |
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#define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) |
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#define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28) |
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#define RPC_DRENR_ADB(o) (((o) & 0x3) << 24) |
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#define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20) |
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#define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16) |
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#define RPC_DRENR_DME BIT(15) |
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#define RPC_DRENR_CDE BIT(14) |
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#define RPC_DRENR_OCDE BIT(12) |
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#define RPC_DRENR_ADE(v) (((v) & 0xF) << 8) |
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#define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4) |
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#define RPC_SMCR 0x0020 /* R/W */ |
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#define RPC_SMCR_SSLKP BIT(8) |
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#define RPC_SMCR_SPIRE BIT(2) |
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#define RPC_SMCR_SPIWE BIT(1) |
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#define RPC_SMCR_SPIE BIT(0) |
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#define RPC_SMCMR 0x0024 /* R/W */ |
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#define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16) |
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#define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0) |
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#define RPC_SMADR 0x0028 /* R/W */ |
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#define RPC_SMOPR 0x002C /* R/W */ |
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#define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0) |
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#define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8) |
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#define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16) |
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#define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24) |
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#define RPC_SMENR 0x0030 /* R/W */ |
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#define RPC_SMENR_CDB(o) (((o) & 0x3) << 30) |
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#define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28) |
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#define RPC_SMENR_ADB(o) (((o) & 0x3) << 24) |
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#define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20) |
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#define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16) |
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#define RPC_SMENR_DME BIT(15) |
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#define RPC_SMENR_CDE BIT(14) |
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#define RPC_SMENR_OCDE BIT(12) |
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#define RPC_SMENR_ADE(v) (((v) & 0xF) << 8) |
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#define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4) |
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#define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0) |
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#define RPC_SMRDR0 0x0038 /* R */ |
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#define RPC_SMRDR1 0x003C /* R */ |
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#define RPC_SMWDR0 0x0040 /* R/W */ |
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#define RPC_SMWDR1 0x0044 /* R/W */ |
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#define RPC_CMNSR 0x0048 /* R */ |
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#define RPC_CMNSR_SSLF BIT(1) |
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#define RPC_CMNSR_TEND BIT(0) |
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#define RPC_DRDMCR 0x0058 /* R/W */ |
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#define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0) |
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#define RPC_DRDRENR 0x005C /* R/W */ |
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#define RPC_DRDRENR_HYPE (0x5 << 12) |
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#define RPC_DRDRENR_ADDRE BIT(8) |
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#define RPC_DRDRENR_OPDRE BIT(4) |
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#define RPC_DRDRENR_DRDRE BIT(0) |
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#define RPC_SMDMCR 0x0060 /* R/W */ |
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#define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0) |
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#define RPC_SMDRENR 0x0064 /* R/W */ |
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#define RPC_SMDRENR_HYPE (0x5 << 12) |
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#define RPC_SMDRENR_ADDRE BIT(8) |
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#define RPC_SMDRENR_OPDRE BIT(4) |
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#define RPC_SMDRENR_SPIDRE BIT(0) |
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#define RPC_PHYCNT 0x007C /* R/W */ |
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#define RPC_PHYCNT_CAL BIT(31) |
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#define PRC_PHYCNT_OCTA_AA BIT(22) |
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#define PRC_PHYCNT_OCTA_SA BIT(23) |
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#define PRC_PHYCNT_EXDS BIT(21) |
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#define RPC_PHYCNT_OCT BIT(20) |
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#define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) |
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#define RPC_PHYCNT_WBUF2 BIT(4) |
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#define RPC_PHYCNT_WBUF BIT(2) |
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#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) |
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#define RPC_PHYINT 0x0088 /* R/W */ |
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#define RPC_PHYINT_RSTEN BIT(18) |
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#define RPC_PHYINT_WPEN BIT(17) |
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#define RPC_PHYINT_INTEN BIT(16) |
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#define RPC_PHYINT_RST BIT(2) |
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#define RPC_PHYINT_WP BIT(1) |
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#define RPC_PHYINT_INT BIT(0) |
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#define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */ |
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#define RPC_WBUF_SIZE 0x100 |
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DECLARE_GLOBAL_DATA_PTR; |
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struct rpc_spi_platdata { |
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fdt_addr_t regs; |
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fdt_addr_t extr; |
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s32 freq; /* Default clock freq, -1 for none */ |
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}; |
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struct rpc_spi_priv { |
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fdt_addr_t regs; |
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fdt_addr_t extr; |
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struct clk clk; |
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u8 cmdcopy[8]; |
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u32 cmdlen; |
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bool cmdstarted; |
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}; |
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static int rpc_spi_wait_sslf(struct udevice *dev) |
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{ |
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struct rpc_spi_priv *priv = dev_get_priv(dev->parent); |
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return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_SSLF, |
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false, 1000, false); |
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} |
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static int rpc_spi_wait_tend(struct udevice *dev) |
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{ |
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struct rpc_spi_priv *priv = dev_get_priv(dev->parent); |
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return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_TEND, |
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true, 1000, false); |
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} |
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static void rpc_spi_flush_read_cache(struct udevice *dev) |
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{ |
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struct udevice *bus = dev->parent; |
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struct rpc_spi_priv *priv = dev_get_priv(bus); |
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/* Flush read cache */ |
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writel(RPC_DRCR_SSLN | RPC_DRCR_RBURST(0x1f) | |
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RPC_DRCR_RCF | RPC_DRCR_RBE | RPC_DRCR_SSLE, |
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priv->regs + RPC_DRCR); |
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readl(priv->regs + RPC_DRCR); |
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} |
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static int rpc_spi_claim_bus(struct udevice *dev, bool manual) |
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{ |
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struct udevice *bus = dev->parent; |
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struct rpc_spi_priv *priv = dev_get_priv(bus); |
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/*
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* NOTE: The 0x260 are undocumented bits, but they must be set. |
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* NOTE: On H3 ES1.x (not supported in mainline U-Boot), the |
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* RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the |
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* RPC_PHYCNT_STRTIM shall be 6. |
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*/ |
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writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260, |
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priv->regs + RPC_PHYCNT); |
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writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE | |
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RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0), |
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priv->regs + RPC_CMNCR); |
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writel(RPC_SSLDR_SPNDL(7) | RPC_SSLDR_SLNDL(7) | |
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RPC_SSLDR_SCKDL(7), priv->regs + RPC_SSLDR); |
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rpc_spi_flush_read_cache(dev); |
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return 0; |
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} |
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static int rpc_spi_release_bus(struct udevice *dev) |
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{ |
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struct udevice *bus = dev->parent; |
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struct rpc_spi_priv *priv = dev_get_priv(bus); |
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/* NOTE: The 0x260 are undocumented bits, but they must be set. */ |
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writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT); |
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rpc_spi_flush_read_cache(dev); |
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return 0; |
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} |
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static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen, |
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const void *dout, void *din, unsigned long flags) |
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{ |
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struct udevice *bus = dev->parent; |
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struct rpc_spi_priv *priv = dev_get_priv(bus); |
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u32 wlen = dout ? (bitlen / 8) : 0; |
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u32 rlen = din ? (bitlen / 8) : 0; |
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u32 wloop = DIV_ROUND_UP(wlen, 4); |
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u32 smenr, smcr, offset; |
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int ret = 0; |
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if (!priv->cmdstarted) { |
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if (!wlen || rlen) |
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BUG(); |
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memcpy(priv->cmdcopy, dout, wlen); |
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priv->cmdlen = wlen; |
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/* Command transfer start */ |
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priv->cmdstarted = true; |
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if (!(flags & SPI_XFER_END)) |
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return 0; |
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} |
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offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) | |
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(priv->cmdcopy[3] << 0); |
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smenr = 0; |
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if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) { |
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if (wlen && flags == SPI_XFER_END) |
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smenr = RPC_SMENR_SPIDE(0xf); |
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rpc_spi_claim_bus(dev, true); |
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writel(0, priv->regs + RPC_SMCR); |
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if (priv->cmdlen >= 1) { /* Command(1) */ |
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writel(RPC_SMCMR_CMD(priv->cmdcopy[0]), |
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priv->regs + RPC_SMCMR); |
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smenr |= RPC_SMENR_CDE; |
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} else { |
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writel(0, priv->regs + RPC_SMCMR); |
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} |
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if (priv->cmdlen >= 4) { /* Address(3) */ |
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writel(offset, priv->regs + RPC_SMADR); |
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smenr |= RPC_SMENR_ADE(7); |
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} else { |
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writel(0, priv->regs + RPC_SMADR); |
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} |
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if (priv->cmdlen >= 5) { /* Dummy(n) */ |
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writel(8 * (priv->cmdlen - 4) - 1, |
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priv->regs + RPC_SMDMCR); |
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smenr |= RPC_SMENR_DME; |
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} else { |
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writel(0, priv->regs + RPC_SMDMCR); |
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} |
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writel(0, priv->regs + RPC_SMOPR); |
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writel(0, priv->regs + RPC_SMDRENR); |
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if (wlen && flags == SPI_XFER_END) { |
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u32 *datout = (u32 *)dout; |
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while (wloop--) { |
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smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE; |
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if (wloop >= 1) |
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smcr |= RPC_SMCR_SSLKP; |
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writel(smenr, priv->regs + RPC_SMENR); |
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writel(*datout, priv->regs + RPC_SMWDR0); |
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writel(smcr, priv->regs + RPC_SMCR); |
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ret = rpc_spi_wait_tend(dev); |
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if (ret) |
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goto err; |
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datout++; |
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smenr = RPC_SMENR_SPIDE(0xf); |
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} |
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ret = rpc_spi_wait_sslf(dev); |
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} else { |
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writel(smenr, priv->regs + RPC_SMENR); |
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writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR); |
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ret = rpc_spi_wait_tend(dev); |
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} |
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} else { /* Read data only, using DRx ext access */ |
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rpc_spi_claim_bus(dev, false); |
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if (priv->cmdlen >= 1) { /* Command(1) */ |
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writel(RPC_DRCMR_CMD(priv->cmdcopy[0]), |
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priv->regs + RPC_DRCMR); |
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smenr |= RPC_DRENR_CDE; |
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} else { |
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writel(0, priv->regs + RPC_DRCMR); |
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} |
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if (priv->cmdlen >= 4) /* Address(3) */ |
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smenr |= RPC_DRENR_ADE(7); |
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if (priv->cmdlen >= 5) { /* Dummy(n) */ |
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writel(8 * (priv->cmdlen - 4) - 1, |
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priv->regs + RPC_DRDMCR); |
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smenr |= RPC_DRENR_DME; |
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} else { |
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writel(0, priv->regs + RPC_DRDMCR); |
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} |
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writel(0, priv->regs + RPC_DROPR); |
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writel(smenr, priv->regs + RPC_DRENR); |
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if (rlen) |
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memcpy_fromio(din, (void *)(priv->extr + offset), rlen); |
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else |
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readl(priv->extr); /* Dummy read */ |
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} |
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err: |
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priv->cmdstarted = false; |
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rpc_spi_release_bus(dev); |
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return ret; |
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} |
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static int rpc_spi_set_speed(struct udevice *bus, uint speed) |
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{ |
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/* This is a SPI NOR controller, do nothing. */ |
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return 0; |
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} |
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static int rpc_spi_set_mode(struct udevice *bus, uint mode) |
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{ |
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/* This is a SPI NOR controller, do nothing. */ |
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return 0; |
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} |
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static int rpc_spi_bind(struct udevice *parent) |
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{ |
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const void *fdt = gd->fdt_blob; |
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ofnode node; |
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int ret, off; |
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/*
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* Check if there are any SPI NOR child nodes, if so, bind as |
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* this controller will be operated in SPI mode. |
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*/ |
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dev_for_each_subnode(node, parent) { |
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off = ofnode_to_offset(node); |
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ret = fdt_node_check_compatible(fdt, off, "spi-flash"); |
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if (!ret) |
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return 0; |
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ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor"); |
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if (!ret) |
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return 0; |
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} |
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return -ENODEV; |
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} |
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static int rpc_spi_probe(struct udevice *dev) |
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{ |
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struct rpc_spi_platdata *plat = dev_get_platdata(dev); |
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struct rpc_spi_priv *priv = dev_get_priv(dev); |
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priv->regs = plat->regs; |
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priv->extr = plat->extr; |
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clk_enable(&priv->clk); |
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return 0; |
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} |
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static int rpc_spi_ofdata_to_platdata(struct udevice *bus) |
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{ |
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struct rpc_spi_platdata *plat = dev_get_platdata(bus); |
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struct rpc_spi_priv *priv = dev_get_priv(bus); |
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int ret; |
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plat->regs = dev_read_addr_index(bus, 0); |
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plat->extr = dev_read_addr_index(bus, 1); |
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ret = clk_get_by_index(bus, 0, &priv->clk); |
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if (ret < 0) { |
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printf("%s: Could not get clock for %s: %d\n", |
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__func__, bus->name, ret); |
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return ret; |
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} |
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plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000); |
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return 0; |
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} |
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static const struct dm_spi_ops rpc_spi_ops = { |
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.xfer = rpc_spi_xfer, |
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.set_speed = rpc_spi_set_speed, |
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.set_mode = rpc_spi_set_mode, |
||||
}; |
||||
|
||||
static const struct udevice_id rpc_spi_ids[] = { |
||||
{ .compatible = "renesas,rpc-r8a7795" }, |
||||
{ .compatible = "renesas,rpc-r8a7796" }, |
||||
{ .compatible = "renesas,rpc-r8a77965" }, |
||||
{ .compatible = "renesas,rpc-r8a77970" }, |
||||
{ .compatible = "renesas,rpc-r8a77995" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(rpc_spi) = { |
||||
.name = "rpc_spi", |
||||
.id = UCLASS_SPI, |
||||
.of_match = rpc_spi_ids, |
||||
.ops = &rpc_spi_ops, |
||||
.ofdata_to_platdata = rpc_spi_ofdata_to_platdata, |
||||
.platdata_auto_alloc_size = sizeof(struct rpc_spi_platdata), |
||||
.priv_auto_alloc_size = sizeof(struct rpc_spi_priv), |
||||
.bind = rpc_spi_bind, |
||||
.probe = rpc_spi_probe, |
||||
}; |
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Reference in new issue