Add MAC support. Use PHY, connected to RGMII1 as a default Eth adapter, by appropriate setting of 'cpsw_data.active_slave'. 'cpsw_phy' env variable can override this setting. Set the MAC addresses in the U-Boot environment. The addresses are retrieved from the on-board EEPROM or from the SOC's MAC fuses. Set the following PHYs RGMII clock delays: - Enable RX delay - Disable TX delay Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> [uri.mashiach@compulab.co.il: add RGMII clock delays] Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com>master
Dmitry Lifshitz
8 years ago
committed by
Tom Rini
parent
965c509f0a
commit
fc300e2c5d
@ -0,0 +1,198 @@ |
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/*
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* Ethernet specific code for CompuLab CL-SOM-AM57x module |
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* |
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* (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
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* |
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* Author: Uri Mashiach <uri.mashiach@compulab.co.il> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <cpsw.h> |
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#include <miiphy.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/sys_proto.h> |
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#include "../common/eeprom.h" |
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static void cpsw_control(int enabled) |
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{ |
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/* VTP can be added here */ |
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} |
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static struct cpsw_slave_data cl_som_am57x_cpsw_slaves[] = { |
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{ |
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.slave_reg_ofs = 0x208, |
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.sliver_reg_ofs = 0xd80, |
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.phy_addr = 0, |
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.phy_if = PHY_INTERFACE_MODE_RMII, |
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}, |
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{ |
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.slave_reg_ofs = 0x308, |
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.sliver_reg_ofs = 0xdc0, |
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.phy_addr = 1, |
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.phy_if = PHY_INTERFACE_MODE_RMII, |
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}, |
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}; |
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static struct cpsw_platform_data cl_som_am57_cpsw_data = { |
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.mdio_base = CPSW_MDIO_BASE, |
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.cpsw_base = CPSW_BASE, |
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.mdio_div = 0xff, |
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.channels = 8, |
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.cpdma_reg_ofs = 0x800, |
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.slaves = 2, |
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.slave_data = cl_som_am57x_cpsw_slaves, |
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.ale_reg_ofs = 0xd00, |
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.ale_entries = 1024, |
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.host_port_reg_ofs = 0x108, |
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.hw_stats_reg_ofs = 0x900, |
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.bd_ram_ofs = 0x2000, |
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.mac_control = (1 << 5), |
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.control = cpsw_control, |
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.host_port_num = 0, |
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.version = CPSW_CTRL_VERSION_2, |
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}; |
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/*
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* cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address. |
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* The information is retrieved from the SOC's registers. |
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* @buff: read buffer. |
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* @port_num: port number. |
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*/ |
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static void cl_som_am57x_efuse_read_mac_addr(uchar *buff, uint port_num) |
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{ |
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uint32_t mac_hi, mac_lo; |
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if (port_num) { |
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mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); |
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mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); |
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} else { |
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mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); |
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mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); |
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} |
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buff[0] = (mac_hi & 0xFF0000) >> 16; |
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buff[1] = (mac_hi & 0xFF00) >> 8; |
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buff[2] = mac_hi & 0xFF; |
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buff[3] = (mac_lo & 0xFF0000) >> 16; |
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buff[4] = (mac_lo & 0xFF00) >> 8; |
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buff[5] = mac_lo & 0xFF; |
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} |
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/*
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* cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot |
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* environment. |
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* The address is retrieved retrieved from an EEPROM field or from the |
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* SOC's registers. |
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* @env_name: U-Boot environment name. |
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* @field_name: EEPROM field name. |
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* @port_num: SOC's port number. |
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*/ |
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static int cl_som_am57x_handle_mac_address(char *env_name, uint port_num) |
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{ |
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int ret; |
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uint8_t enetaddr[6]; |
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ret = eth_getenv_enetaddr(env_name, enetaddr); |
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if (ret) |
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return 0; |
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ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); |
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if (ret || !is_valid_ethaddr(enetaddr)) |
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cl_som_am57x_efuse_read_mac_addr(enetaddr, port_num); |
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if (!is_valid_ethaddr(enetaddr)) |
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return -1; |
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ret = eth_setenv_enetaddr(env_name, enetaddr); |
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if (ret) |
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printf("cl-som-am57x: Failed to set Eth port %d MAC address\n", |
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port_num); |
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return ret; |
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} |
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#define CL_SOM_AM57X_PHY_ADDR2 0x01 |
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#define AR8033_PHY_DEBUG_ADDR_REG 0x1d |
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#define AR8033_PHY_DEBUG_DATA_REG 0x1e |
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#define AR8033_DEBUG_RGMII_RX_CLK_DLY_REG 0x00 |
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#define AR8033_DEBUG_RGMII_TX_CLK_DLY_REG 0x05 |
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#define AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK (1 << 15) |
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#define AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK (1 << 8) |
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/*
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* cl_som_am57x_rgmii_clk_delay() - Set RGMII clock delay. |
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* Enable RX delay, disable TX delay. |
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*/ |
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static void cl_som_am57x_rgmii_clk_delay(void) |
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{ |
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uint16_t mii_reg_val; |
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const char *devname; |
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devname = miiphy_get_current_dev(); |
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/* PHY 2 */ |
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miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG, |
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AR8033_DEBUG_RGMII_RX_CLK_DLY_REG); |
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miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, |
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&mii_reg_val); |
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mii_reg_val |= AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK; |
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miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, |
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mii_reg_val); |
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miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG, |
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AR8033_DEBUG_RGMII_TX_CLK_DLY_REG); |
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miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, |
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&mii_reg_val); |
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mii_reg_val &= ~AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK; |
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miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, |
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mii_reg_val); |
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} |
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#define CL_SOM_AM57X_GPIO_PHY1_RST 92 /* GPIO3_28 */ |
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#define CL_SOM_AM57X_RGMII_PORT1 1 |
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int board_eth_init(bd_t *bis) |
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{ |
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int ret; |
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uint32_t ctrl_val; |
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char *cpsw_phy_envval; |
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int cpsw_act_phy = 1; |
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/* SB-SOM-AM57x primary Eth (P21) is routed to RGMII1 */ |
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ret = cl_som_am57x_handle_mac_address("ethaddr", |
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CL_SOM_AM57X_RGMII_PORT1); |
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if (ret) |
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return -1; |
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/* Select RGMII for GMII1_SEL */ |
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ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); |
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ctrl_val |= 0x22; |
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writel(ctrl_val, (*ctrl)->control_core_control_io1); |
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mdelay(10); |
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gpio_request(CL_SOM_AM57X_GPIO_PHY1_RST, "phy1_rst"); |
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gpio_direction_output(CL_SOM_AM57X_GPIO_PHY1_RST, 0); |
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mdelay(20); |
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gpio_set_value(CL_SOM_AM57X_GPIO_PHY1_RST, 1); |
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mdelay(20); |
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cpsw_phy_envval = getenv("cpsw_phy"); |
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if (cpsw_phy_envval != NULL) |
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cpsw_act_phy = simple_strtoul(cpsw_phy_envval, NULL, 0); |
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cl_som_am57_cpsw_data.active_slave = cpsw_act_phy; |
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ret = cpsw_register(&cl_som_am57_cpsw_data); |
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if (ret < 0) |
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printf("Error %d registering CPSW switch\n", ret); |
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/* Set RGMII clock delay */ |
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cl_som_am57x_rgmii_clk_delay(); |
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return ret; |
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} |
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