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@ -64,7 +64,7 @@ static int sgmii_riser_phy_addr[] = { |
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}; |
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/* Slot2 does not have EMI connections */ |
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#define EMI_NONE 0xFFFFFFFF |
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#define EMI_NONE 0xFF |
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#define EMI1_SLOT1 0 |
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#define EMI1_SLOT2 1 |
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#define EMI1_SLOT3 2 |
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@ -470,7 +470,49 @@ static void initialize_dpmac_to_slot(void) |
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} |
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break; |
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case 0x39: |
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printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
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serdes1_prtcl); |
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if (hwconfig_f("xqsgmii", env_hwconfig)) { |
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lane_to_slot_fsm1[0] = EMI1_SLOT3; |
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lane_to_slot_fsm1[1] = EMI1_SLOT3; |
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lane_to_slot_fsm1[2] = EMI1_SLOT3; |
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lane_to_slot_fsm1[3] = EMI_NONE; |
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} else { |
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lane_to_slot_fsm1[0] = EMI_NONE; |
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lane_to_slot_fsm1[1] = EMI_NONE; |
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lane_to_slot_fsm1[2] = EMI_NONE; |
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lane_to_slot_fsm1[3] = EMI_NONE; |
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} |
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lane_to_slot_fsm1[4] = EMI1_SLOT3; |
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lane_to_slot_fsm1[5] = EMI1_SLOT3; |
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lane_to_slot_fsm1[6] = EMI1_SLOT3; |
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lane_to_slot_fsm1[7] = EMI_NONE; |
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break; |
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case 0x4D: |
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printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
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serdes1_prtcl); |
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if (hwconfig_f("xqsgmii", env_hwconfig)) { |
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lane_to_slot_fsm1[0] = EMI1_SLOT3; |
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lane_to_slot_fsm1[1] = EMI1_SLOT3; |
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lane_to_slot_fsm1[2] = EMI_NONE; |
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lane_to_slot_fsm1[3] = EMI_NONE; |
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} else { |
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lane_to_slot_fsm1[0] = EMI_NONE; |
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lane_to_slot_fsm1[1] = EMI_NONE; |
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lane_to_slot_fsm1[2] = EMI_NONE; |
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lane_to_slot_fsm1[3] = EMI_NONE; |
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} |
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lane_to_slot_fsm1[4] = EMI1_SLOT3; |
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lane_to_slot_fsm1[5] = EMI1_SLOT3; |
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lane_to_slot_fsm1[6] = EMI_NONE; |
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lane_to_slot_fsm1[7] = EMI_NONE; |
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break; |
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case 0x2A: |
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case 0x4B: |
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case 0x4C: |
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printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
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serdes1_prtcl); |
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break; |
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@ -505,6 +547,38 @@ static void initialize_dpmac_to_slot(void) |
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lane_to_slot_fsm2[7] = EMI1_SLOT6; |
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} |
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break; |
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case 0x47: |
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printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", |
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serdes2_prtcl); |
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lane_to_slot_fsm2[0] = EMI_NONE; |
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lane_to_slot_fsm2[1] = EMI1_SLOT5; |
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lane_to_slot_fsm2[2] = EMI1_SLOT5; |
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lane_to_slot_fsm2[3] = EMI1_SLOT5; |
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if (hwconfig_f("xqsgmii", env_hwconfig)) { |
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lane_to_slot_fsm2[4] = EMI_NONE; |
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lane_to_slot_fsm2[5] = EMI1_SLOT5; |
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lane_to_slot_fsm2[6] = EMI1_SLOT5; |
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lane_to_slot_fsm2[7] = EMI1_SLOT5; |
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} |
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break; |
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case 0x57: |
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printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", |
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serdes2_prtcl); |
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if (hwconfig_f("xqsgmii", env_hwconfig)) { |
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lane_to_slot_fsm2[0] = EMI_NONE; |
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lane_to_slot_fsm2[1] = EMI_NONE; |
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lane_to_slot_fsm2[2] = EMI_NONE; |
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lane_to_slot_fsm2[3] = EMI_NONE; |
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} |
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lane_to_slot_fsm2[4] = EMI_NONE; |
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lane_to_slot_fsm2[5] = EMI_NONE; |
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lane_to_slot_fsm2[6] = EMI1_SLOT5; |
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lane_to_slot_fsm2[7] = EMI1_SLOT5; |
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break; |
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default: |
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printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", |
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__func__ , serdes2_prtcl); |
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@ -537,8 +611,10 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) |
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switch (serdes1_prtcl) { |
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case 0x07: |
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case 0x39: |
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case 0x4D: |
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lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1); |
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lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id); |
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slot = lane_to_slot_fsm1[lane]; |
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switch (++slot) { |
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@ -559,6 +635,26 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) |
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wriop_set_mdio(dpmac_id, bus); |
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break; |
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case 3: |
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if (slot == EMI_NONE) |
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return; |
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if (serdes1_prtcl == 0x39) { |
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wriop_set_phy_address(dpmac_id, |
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riser_phy_addr[dpmac_id - 2]); |
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if (dpmac_id >= 6 && hwconfig_f("xqsgmii", |
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env_hwconfig)) |
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wriop_set_phy_address(dpmac_id, |
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riser_phy_addr[dpmac_id - 3]); |
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} else { |
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wriop_set_phy_address(dpmac_id, |
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riser_phy_addr[dpmac_id - 2]); |
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if (dpmac_id >= 7 && hwconfig_f("xqsgmii", |
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env_hwconfig)) |
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wriop_set_phy_address(dpmac_id, |
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riser_phy_addr[dpmac_id - 3]); |
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} |
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dpmac_info[dpmac_id].board_mux = EMI1_SLOT3; |
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bus = mii_dev_for_muxval(EMI1_SLOT3); |
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wriop_set_mdio(dpmac_id, bus); |
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break; |
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case 4: |
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break; |
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@ -579,6 +675,8 @@ serdes2: |
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case 0x07: |
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case 0x08: |
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case 0x49: |
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case 0x47: |
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case 0x57: |
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lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 + |
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(dpmac_id - 9)); |
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slot = lane_to_slot_fsm2[lane]; |
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@ -597,7 +695,23 @@ serdes2: |
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wriop_set_mdio(dpmac_id, bus); |
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break; |
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case 5: |
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break; |
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if (slot == EMI_NONE) |
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return; |
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if (serdes2_prtcl == 0x47) { |
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wriop_set_phy_address(dpmac_id, |
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riser_phy_addr[dpmac_id - 10]); |
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if (dpmac_id >= 14 && hwconfig_f("xqsgmii", |
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env_hwconfig)) |
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wriop_set_phy_address(dpmac_id, |
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riser_phy_addr[dpmac_id - 11]); |
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} else { |
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wriop_set_phy_address(dpmac_id, |
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riser_phy_addr[dpmac_id - 11]); |
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} |
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dpmac_info[dpmac_id].board_mux = EMI1_SLOT5; |
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bus = mii_dev_for_muxval(EMI1_SLOT5); |
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wriop_set_mdio(dpmac_id, bus); |
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break; |
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case 6: |
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/* Slot housing a SGMII riser card? */ |
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wriop_set_phy_address(dpmac_id, |
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@ -691,6 +805,8 @@ void ls2080a_handle_phy_interface_xsgmii(int i) |
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switch (serdes1_prtcl) { |
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case 0x2A: |
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case 0x4B: |
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case 0x4C: |
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/*
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* XFI does not need a PHY to work, but to avoid U-Boot use |
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* default PHY address which is zero to a MAC when it found |
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