Tom Rini
9 years ago
commit
fc83410095
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,12 @@ |
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if TARGET_PORTER |
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config SYS_BOARD |
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default "porter" |
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config SYS_VENDOR |
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default "renesas" |
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config SYS_CONFIG_NAME |
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default "porter" |
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endif |
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@ -0,0 +1,6 @@ |
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PORTER BOARD |
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M: Cogent Embedded, Inc. <source@cogentembedded.com> |
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S: Maintained |
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F: board/renesas/porter/ |
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F: include/configs/porter.h |
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F: configs/porter_defconfig |
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@ -0,0 +1,10 @@ |
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#
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# board/renesas/porter/Makefile
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#
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# Copyright (C) 2015 Renesas Electronics Corporation
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# Copyright (C) 2015 Cogent Embedded, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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obj-y := porter.o qos.o ../rcar-gen2-common/common.o
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@ -0,0 +1,228 @@ |
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/*
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* board/renesas/porter/porter.c |
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* |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* Copyright (C) 2015 Cogent Embedded, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <dm.h> |
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#include <dm/platform_data/serial_sh.h> |
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#include <asm/processor.h> |
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#include <asm/mach-types.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/rmobile.h> |
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#include <asm/arch/rcar-mstp.h> |
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#include <asm/arch/sh_sdhi.h> |
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#include <netdev.h> |
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#include <miiphy.h> |
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#include <i2c.h> |
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#include <div64.h> |
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#include "qos.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#define CLK2MHZ(clk) (clk / 1000 / 1000) |
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void s_init(void) |
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{ |
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
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u32 stc; |
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/* Watchdog init */ |
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writel(0xA5A5A500, &rwdt->rwtcsra); |
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writel(0xA5A5A500, &swdt->swtcsra); |
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/* CPU frequency setting. Set to 1.5GHz */ |
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stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; |
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); |
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/* QoS */ |
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qos_init(); |
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} |
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#define TMU0_MSTP125 (1 << 25) |
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#define SDHI0_MSTP314 (1 << 14) |
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#define SDHI2_MSTP311 (1 << 11) |
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#define SCIF0_MSTP721 (1 << 21) |
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#define ETHER_MSTP813 (1 << 13) |
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#define SD2CKCR 0xE615026C |
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#define SD_97500KHZ 0x7 |
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int board_early_init_f(void) |
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{ |
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
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/* SCIF0 */ |
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); |
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/* ETHER */ |
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); |
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/* SDHI */ |
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP311); |
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/*
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* SD0 clock is set to 97.5MHz by default. |
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* Set SD2 to the 97.5MHz as well. |
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*/ |
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writel(SD_97500KHZ, SD2CKCR); |
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return 0; |
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} |
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/* LSI pin pull-up control */ |
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#define PUPR5 0xe6060114 |
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#define PUPR5_ETH 0x3FFC0000 |
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#define PUPR5_ETH_MAGIC (1 << 27) |
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int board_init(void) |
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{ |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
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/* Init PFC controller */ |
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r8a7791_pinmux_init(); |
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/* Ether Enable */ |
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gpio_request(GPIO_FN_ETH_CRS_DV, NULL); |
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gpio_request(GPIO_FN_ETH_RX_ER, NULL); |
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gpio_request(GPIO_FN_ETH_RXD0, NULL); |
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gpio_request(GPIO_FN_ETH_RXD1, NULL); |
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gpio_request(GPIO_FN_ETH_LINK, NULL); |
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gpio_request(GPIO_FN_ETH_REFCLK, NULL); |
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gpio_request(GPIO_FN_ETH_MDIO, NULL); |
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gpio_request(GPIO_FN_ETH_TXD1, NULL); |
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gpio_request(GPIO_FN_ETH_TX_EN, NULL); |
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gpio_request(GPIO_FN_ETH_TXD0, NULL); |
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gpio_request(GPIO_FN_ETH_MDC, NULL); |
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gpio_request(GPIO_FN_IRQ0, NULL); |
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); |
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gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ |
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); |
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gpio_direction_output(GPIO_GP_5_22, 0); |
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mdelay(20); |
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gpio_set_value(GPIO_GP_5_22, 1); |
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udelay(1); |
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return 0; |
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} |
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#define CXR24 0xEE7003C0 /* MAC address high register */ |
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#define CXR25 0xEE7003C8 /* MAC address low register */ |
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int board_eth_init(bd_t *bis) |
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{ |
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#ifdef CONFIG_SH_ETHER |
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int ret = -ENODEV; |
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u32 val; |
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unsigned char enetaddr[6]; |
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ret = sh_eth_initialize(bis); |
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if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
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return ret; |
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/* Set Mac address */ |
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val = enetaddr[0] << 24 | enetaddr[1] << 16 | |
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enetaddr[2] << 8 | enetaddr[3]; |
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writel(val, CXR24); |
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val = enetaddr[4] << 8 | enetaddr[5]; |
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writel(val, CXR25); |
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return ret; |
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#else |
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return 0; |
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#endif |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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int ret = -ENODEV; |
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#ifdef CONFIG_SH_SDHI |
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gpio_request(GPIO_FN_SD0_DATA0, NULL); |
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gpio_request(GPIO_FN_SD0_DATA1, NULL); |
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gpio_request(GPIO_FN_SD0_DATA2, NULL); |
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gpio_request(GPIO_FN_SD0_DATA3, NULL); |
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gpio_request(GPIO_FN_SD0_CLK, NULL); |
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gpio_request(GPIO_FN_SD0_CMD, NULL); |
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gpio_request(GPIO_FN_SD0_CD, NULL); |
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gpio_request(GPIO_FN_SD2_DATA0, NULL); |
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gpio_request(GPIO_FN_SD2_DATA1, NULL); |
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gpio_request(GPIO_FN_SD2_DATA2, NULL); |
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gpio_request(GPIO_FN_SD2_DATA3, NULL); |
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gpio_request(GPIO_FN_SD2_CLK, NULL); |
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gpio_request(GPIO_FN_SD2_CMD, NULL); |
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gpio_request(GPIO_FN_SD2_CD, NULL); |
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/* SDHI 0 */ |
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gpio_request(GPIO_GP_2_12, NULL); |
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gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ |
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, |
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SH_SDHI_QUIRK_16BIT_BUF); |
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if (ret) |
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return ret; |
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/* SDHI 2 */ |
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gpio_request(GPIO_GP_2_26, NULL); |
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gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ |
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); |
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#endif |
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return ret; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
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return 0; |
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} |
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/* porter has KSZ8041RNLI */ |
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#define PHY_CONTROL1 0x1E |
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#define PHY_LED_MODE 0xC0000 |
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#define PHY_LED_MODE_ACK 0x4000 |
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int board_phy_config(struct phy_device *phydev) |
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{ |
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int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); |
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ret &= ~PHY_LED_MODE; |
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ret |= PHY_LED_MODE_ACK; |
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ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); |
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return 0; |
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} |
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const struct rmobile_sysinfo sysinfo = { |
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CONFIG_RMOBILE_BOARD_STRING |
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}; |
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void reset_cpu(ulong addr) |
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{ |
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u8 val; |
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i2c_set_bus_num(2); /* PowerIC connected to ch2 */ |
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i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); |
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val |= 0x02; |
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i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); |
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} |
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static const struct sh_serial_platdata serial_platdata = { |
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.base = SCIF0_BASE, |
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.type = PORT_SCIF, |
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.clk = CONFIG_P_CLK_FREQ, |
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}; |
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U_BOOT_DEVICE(porter_serials) = { |
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.name = "serial_sh", |
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.platdata = &serial_platdata, |
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}; |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,13 @@ |
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/*
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* Copyright (C) 2015 Cogent Embedded, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef __QOS_H__ |
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#define __QOS_H__ |
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void qos_init(void); |
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#endif |
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@ -1,3 +1,6 @@ |
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CONFIG_ARM=y |
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CONFIG_RMOBILE=y |
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CONFIG_TARGET_ALT=y |
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CONFIG_DM=y |
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CONFIG_DM_SERIAL=y |
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CONFIG_SH_SDHI=y |
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@ -1,3 +1,6 @@ |
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CONFIG_ARM=y |
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CONFIG_RMOBILE=y |
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CONFIG_TARGET_GOSE=y |
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CONFIG_DM=y |
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CONFIG_DM_SERIAL=y |
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CONFIG_SH_SDHI=y |
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@ -1,3 +1,6 @@ |
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CONFIG_ARM=y |
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CONFIG_RMOBILE=y |
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CONFIG_TARGET_KOELSCH=y |
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CONFIG_DM=y |
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CONFIG_DM_SERIAL=y |
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CONFIG_SH_SDHI=y |
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@ -1,3 +1,6 @@ |
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CONFIG_ARM=y |
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CONFIG_RMOBILE=y |
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CONFIG_TARGET_LAGER=y |
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CONFIG_DM=y |
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CONFIG_DM_SERIAL=y |
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CONFIG_SH_SDHI=y |
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@ -0,0 +1,6 @@ |
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CONFIG_ARM=y |
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CONFIG_RMOBILE=y |
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CONFIG_TARGET_PORTER=y |
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CONFIG_DM=y |
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CONFIG_DM_SERIAL=y |
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CONFIG_SH_SDHI=y |
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@ -1,3 +1,6 @@ |
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CONFIG_ARM=y |
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CONFIG_RMOBILE=y |
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CONFIG_TARGET_SILK=y |
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CONFIG_DM=y |
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CONFIG_DM_SERIAL=y |
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CONFIG_SH_SDHI=y |
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@ -0,0 +1,112 @@ |
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/*
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* include/configs/porter.h |
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* This file is Porter board configuration. |
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* |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* Copyright (C) 2015 Cogent Embedded, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef __PORTER_H |
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#define __PORTER_H |
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#undef DEBUG |
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#define CONFIG_R8A7791 |
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#define CONFIG_RMOBILE_BOARD_STRING "Porter" |
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#include "rcar-gen2-common.h" |
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#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) |
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#define CONFIG_SYS_TEXT_BASE 0x70000000 |
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#else |
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#define CONFIG_SYS_TEXT_BASE 0xE6304000 |
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#endif |
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#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) |
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#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC |
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#else |
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#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC |
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#endif |
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#define STACK_AREA_SIZE 0xC000 |
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#define LOW_LEVEL_MERAM_STACK \ |
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(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) |
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/* MEMORY */ |
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#define RCAR_GEN2_SDRAM_BASE 0x40000000 |
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#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) |
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#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) |
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/* SCIF */ |
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#define CONFIG_SCIF_CONSOLE |
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/* FLASH */ |
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#define CONFIG_SPI |
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#define CONFIG_SPI_FLASH_BAR |
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#define CONFIG_SH_QSPI |
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#define CONFIG_SPI_FLASH |
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#define CONFIG_SPI_FLASH_SPANSION |
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#define CONFIG_SPI_FLASH_QUAD |
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#define CONFIG_SYS_NO_FLASH |
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/* SH Ether */ |
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#define CONFIG_NET_MULTI |
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#define CONFIG_SH_ETHER |
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#define CONFIG_SH_ETHER_USE_PORT 0 |
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1 |
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII |
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK |
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE |
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#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 |
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#define CONFIG_PHYLIB |
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#define CONFIG_PHY_MICREL |
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#define CONFIG_BITBANGMII |
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#define CONFIG_BITBANGMII_MULTI |
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/* Board Clock */ |
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#define RMOBILE_XTAL_CLK 20000000u |
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK |
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) |
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#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) |
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#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) |
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#define CONFIG_SYS_TMU_CLK_DIV 4 |
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/* i2c */ |
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#define CONFIG_CMD_I2C |
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#define CONFIG_SYS_I2C |
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#define CONFIG_SYS_I2C_SH |
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#define CONFIG_SYS_I2C_SLAVE 0x7F |
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#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 |
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#define CONFIG_SYS_I2C_SH_SPEED0 400000 |
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#define CONFIG_SYS_I2C_SH_SPEED1 400000 |
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#define CONFIG_SYS_I2C_SH_SPEED2 400000 |
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#define CONFIG_SH_I2C_DATA_HIGH 4 |
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#define CONFIG_SH_I2C_DATA_LOW 5 |
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#define CONFIG_SH_I2C_CLOCK 10000000 |
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#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ |
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/* USB */ |
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#define CONFIG_USB_EHCI |
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#define CONFIG_USB_EHCI_RMOBILE |
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
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#define CONFIG_USB_STORAGE |
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/* SD */ |
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#define CONFIG_MMC |
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#define CONFIG_CMD_MMC |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_SH_SDHI_FREQ 97500000 |
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/* Module stop status bits */ |
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/* INTC-RT */ |
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#define CONFIG_SMSTP0_ENA 0x00400000 |
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/* MSIF */ |
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#define CONFIG_SMSTP2_ENA 0x00002000 |
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/* INTC-SYS, IRQC */ |
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#define CONFIG_SMSTP4_ENA 0x00000180 |
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/* SCIF0 */ |
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#define CONFIG_SMSTP7_ENA 0x00200000 |
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#endif /* __PORTER_H */ |
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