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@ -10,7 +10,9 @@ |
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#ifdef CONFIG_MIPS_L2_CACHE |
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#include <asm/cm.h> |
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#endif |
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#include <asm/io.h> |
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#include <asm/mipsregs.h> |
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#include <asm/system.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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@ -96,6 +98,9 @@ static inline unsigned long scache_line_size(void) |
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const unsigned int cache_ops[] = { ops }; \
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unsigned int i; \
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\
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if (!lsize) \
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break; \
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\
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for (; addr <= aend; addr += lsize) { \
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for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
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mips_cache(cache_ops[i], addr); \
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@ -116,19 +121,24 @@ void flush_cache(ulong start_addr, ulong size) |
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/* flush I-cache & D-cache simultaneously */ |
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cache_loop(start_addr, start_addr + size, ilsize, |
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HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); |
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return; |
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goto ops_done; |
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} |
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/* flush D-cache */ |
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cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); |
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/* flush L2 cache */ |
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if (slsize) |
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cache_loop(start_addr, start_addr + size, slsize, |
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HIT_WRITEBACK_INV_SD); |
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cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD); |
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/* flush I-cache */ |
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cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); |
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ops_done: |
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/* ensure cache ops complete before any further memory accesses */ |
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sync(); |
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/* ensure the pipeline doesn't contain now-invalid instructions */ |
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instruction_hazard_barrier(); |
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} |
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void flush_dcache_range(ulong start_addr, ulong stop) |
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@ -143,8 +153,10 @@ void flush_dcache_range(ulong start_addr, ulong stop) |
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cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); |
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/* flush L2 cache */ |
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if (slsize) |
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cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); |
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cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); |
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/* ensure cache ops complete before any further memory accesses */ |
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sync(); |
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} |
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void invalidate_dcache_range(ulong start_addr, ulong stop) |
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@ -157,8 +169,10 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) |
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return; |
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/* invalidate L2 cache */ |
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if (slsize) |
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cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); |
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cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); |
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cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); |
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/* ensure cache ops complete before any further memory accesses */ |
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sync(); |
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} |
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