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@ -13,6 +13,7 @@ |
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#include <memalign.h> |
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#include <phys2bus.h> |
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#include <usbroothubdes.h> |
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#include <wait_bit.h> |
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#include <asm/io.h> |
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#include "dwc2.h" |
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@ -52,27 +53,6 @@ static struct dwc2_priv local; |
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/*
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* DWC2 IP interface |
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*/ |
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static int wait_for_bit(void *reg, const uint32_t mask, bool set) |
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{ |
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unsigned int timeout = 1000000; |
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uint32_t val; |
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while (--timeout) { |
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val = readl(reg); |
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if (!set) |
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val = ~val; |
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if ((val & mask) == mask) |
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return 0; |
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udelay(1); |
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} |
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debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", |
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__func__, reg, mask, set); |
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return -ETIMEDOUT; |
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} |
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/*
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* Initializes the FSLSPClkSel field of the HCFG register |
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@ -117,7 +97,8 @@ static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) |
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writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), |
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®s->grstctl); |
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ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0); |
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ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH, |
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false, 1000, false); |
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if (ret) |
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printf("%s: Timeout!\n", __func__); |
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@ -135,7 +116,8 @@ static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) |
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int ret; |
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writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); |
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ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0); |
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ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH, |
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false, 1000, false); |
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if (ret) |
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printf("%s: Timeout!\n", __func__); |
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@ -152,13 +134,15 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs) |
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int ret; |
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/* Wait for AHB master IDLE state. */ |
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ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1); |
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ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE, |
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true, 1000, false); |
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if (ret) |
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printf("%s: Timeout!\n", __func__); |
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/* Core Soft Reset */ |
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writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); |
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ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0); |
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ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST, |
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false, 1000, false); |
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if (ret) |
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printf("%s: Timeout!\n", __func__); |
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@ -243,8 +227,8 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs *regs) |
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clrsetbits_le32(®s->hc_regs[i].hcchar, |
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DWC2_HCCHAR_EPDIR, |
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DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); |
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ret = wait_for_bit(®s->hc_regs[i].hcchar, |
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DWC2_HCCHAR_CHEN, 0); |
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ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar, |
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DWC2_HCCHAR_CHEN, false, 1000, false); |
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if (ret) |
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printf("%s: Timeout!\n", __func__); |
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} |
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@ -737,7 +721,8 @@ int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle, |
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int ret; |
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uint32_t hcint, hctsiz; |
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ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true); |
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ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true, |
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1000, false); |
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if (ret) |
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return ret; |
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