Tom Rini
9 years ago
commit
fd9102dafe
@ -0,0 +1,157 @@ |
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/* |
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* at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board |
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* |
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* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
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* |
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* Licensed under GPLv2. |
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*/ |
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/dts-v1/; |
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#include "at91sam9g45.dtsi" |
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|
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/ { |
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model = "Bluewater Systems Gurnard"; |
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compatible = "atmel,at91sam9g45", "atmel,at91sam9"; |
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|
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chosen { |
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bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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memory { |
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reg = <0x20000000 0x8000000>; |
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}; |
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|
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clocks { |
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slow_xtal { |
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clock-frequency = <32768>; |
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}; |
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|
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main_xtal { |
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clock-frequency = <18432000>; |
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}; |
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}; |
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|
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ahb { |
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u-boot,dm-pre-reloc; |
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|
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fb@0x00500000 { |
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u-boot,dm-pre-reloc; |
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status = "okay"; |
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display-timings { |
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rev1 { |
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clock-frequency = <4166666>; |
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hactive = <480>; |
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vactive = <272>; |
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hfront-porch = <1>; |
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hback-porch = <1>; |
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hsync-len = <1>; |
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vback-porch = <4>; |
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vfront-porch = <2>; |
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vsync-len = <1>; |
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hsync-active = <0>; |
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vsync-active = <0>; |
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}; |
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|
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rev2 { |
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clock-frequency = <4166666>; |
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hactive = <480>; |
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vactive = <272>; |
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hfront-porch = <2>; |
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hback-porch = <2>; |
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hsync-len = <10>; |
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vback-porch = <2>; |
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vfront-porch = <2>; |
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vsync-len = <10>; |
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hsync-active = <0>; |
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vsync-active = <0>; |
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}; |
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}; |
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}; |
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|
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apb { |
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pinctrl@fffff400 { |
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board { |
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pinctrl_pck0_as_mck: pck0_as_mck { |
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atmel,pins = |
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<AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */ |
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}; |
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|
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}; |
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|
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mmc0_slot1 { |
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pinctrl_board_mmc0_slot1: mmc0_slot1-board { |
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atmel,pins = |
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<AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC9 gpio CD pin pull up and deglitch */ |
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}; |
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}; |
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}; |
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|
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dbgu: serial@ffffee00 { |
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status = "okay"; |
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}; |
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|
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macb0: ethernet@fffbc000 { |
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phy-mode = "rmii"; |
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status = "okay"; |
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}; |
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|
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mmc0: mmc@fff80000 { |
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pinctrl-0 = < |
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&pinctrl_board_mmc0_slot1 |
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&pinctrl_mmc0_slot0_clk_cmd_dat0 |
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&pinctrl_mmc0_slot0_dat1_3>; |
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status = "okay"; |
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slot@1 { |
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reg = <1>; |
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bus-width = <4>; |
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cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; |
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}; |
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}; |
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|
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ssc0: ssc@fff9c000 { |
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status = "okay"; |
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pinctrl-0 = <&pinctrl_ssc0_tx>; |
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}; |
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|
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spi0: spi@fffa4000 { |
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cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; |
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mtd_dataflash@0 { |
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compatible = "atmel,at45", "atmel,dataflash"; |
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spi-max-frequency = <50000000>; |
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reg = <1>; |
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}; |
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}; |
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|
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shdwc@fffffd10 { |
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atmel,wakeup-counter = <10>; |
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atmel,wakeup-rtt-timer; |
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}; |
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|
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rtc@fffffd20 { |
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atmel,rtt-rtc-time-reg = <&gpbr 0x0>; |
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status = "okay"; |
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}; |
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|
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watchdog@fffffd40 { |
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status = "okay"; |
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}; |
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|
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gpbr: syscon@fffffd60 { |
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status = "okay"; |
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}; |
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}; |
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nand0: nand@40000000 { |
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nand-bus-width = <8>; |
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nand-ecc-mode = "hardware"; |
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nand-on-flash-bbt; |
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status = "okay"; |
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}; |
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|
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usb1: ehci@00800000 { |
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atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; |
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status = "okay"; |
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}; |
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}; |
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|
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}; |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,71 @@ |
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/*
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* Copyright (C) 2005 Ivan Kokshaysky |
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* Copyright (C) SAN People |
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* |
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* Real Time Clock (RTC) - System peripheral registers. |
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* Based on AT91RM9200 datasheet revision E. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef AT91_RTC_H |
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#define AT91_RTC_H |
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|
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/* Control Register */ |
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#define AT91_RTC_CR (ATMEL_BASE_RTC + 0x00) |
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#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time */ |
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#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar */ |
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#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ |
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#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) |
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#define AT91_RTC_TIMEVSEL_HOUR (1 << 8) |
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#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) |
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#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) |
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#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ |
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#define AT91_RTC_CALEVSEL_WEEK (0 << 16) |
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#define AT91_RTC_CALEVSEL_MONTH (1 << 16) |
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#define AT91_RTC_CALEVSEL_YEAR (2 << 16) |
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|
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#define AT91_RTC_MR (ATMEL_BASE_RTC + 0x04) /* Mode Register */ |
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#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ |
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|
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#define AT91_RTC_TIMR (ATMEL_BASE_RTC + 0x08) /* Time Register */ |
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#define AT91_RTC_SEC (0x7f << 0) /* Current Second */ |
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#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ |
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#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ |
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#define AT91_RTC_AMPM (1 << 22) /* AM/PM */ |
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|
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#define AT91_RTC_CALR (ATMEL_BASE_RTC + 0x0c) /* Calendar Register */ |
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#define AT91_RTC_CENT (0x7f << 0) /* Current Century */ |
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#define AT91_RTC_YEAR (0xff << 8) /* Current Year */ |
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#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ |
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#define AT91_RTC_DAY (7 << 21) /* Current Day */ |
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#define AT91_RTC_DATE (0x3f << 24) /* Current Date */ |
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|
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#define AT91_RTC_TIMALR (ATMEL_BASE_RTC + 0x10) /* Time Alarm */ |
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#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enab */ |
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#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enab */ |
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#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ |
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|
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#define AT91_RTC_CALALR (ATMEL_BASE_RTC + 0x14) /* Calendar Alarm */ |
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#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ |
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#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ |
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|
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#define AT91_RTC_SR (ATMEL_BASE_RTC + 0x18) /* Status Register */ |
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#define AT91_RTC_ACKUPD (1 << 0) /* Ack for Update */ |
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#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ |
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#define AT91_RTC_SECEV (1 << 2) /* Second Event */ |
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#define AT91_RTC_TIMEV (1 << 3) /* Time Event */ |
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#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ |
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|
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#define AT91_RTC_SCCR (ATMEL_BASE_RTC + 0x1c) /* Status Clear Cmd */ |
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#define AT91_RTC_IER (ATMEL_BASE_RTC + 0x20) /* Interrupt Enable */ |
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#define AT91_RTC_IDR (ATMEL_BASE_RTC + 0x24) /* Interrupt Disable */ |
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#define AT91_RTC_IMR (ATMEL_BASE_RTC + 0x28) /* Interrupt Mask */ |
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#define AT91_RTC_VER (ATMEL_BASE_RTC + 0x2c) /* Valid Entry */ |
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#define AT91_RTC_NVTIM (1 << 0) /* Non-valid Time */ |
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#define AT91_RTC_NVCAL (1 << 1) /* Non-valid Calendar */ |
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#define AT91_RTC_NVTIMALR (1 << 2) /* .. Time Alarm */ |
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#define AT91_RTC_NVCALALR (1 << 3) /* .. Calendar Alarm */ |
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#endif |
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@ -0,0 +1,21 @@ |
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/*
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* Copyright (C) 2016 Google, Inc |
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* Written by Simon Glass <sjg@chromium.org> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef AT91_SCK_H |
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#define AT91_SCK_H |
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/*
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* SCKCR flags |
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*/ |
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#define AT91SAM9G45_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ |
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#define AT91SAM9G45_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ |
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#define AT91SAM9G45_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ |
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#define AT91SAM9G45_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ |
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#define AT91SAM9G45_SCKCR_OSCSEL_RC (0 << 3) |
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#define AT91SAM9G45_SCKCR_OSCSEL_32 (1 << 3) |
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#endif |
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@ -0,0 +1,25 @@ |
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/*
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* Boot mode definitions for the SAMA5Dx SoC |
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* |
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* Copyright (C) 2016 Marek Vasut <marex@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __SAMA5_BOOT_H |
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#define __SAMA5_BOOT_H |
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/* Boot modes stored by BootROM in r4 */ |
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#define ATMEL_SAMA5_BOOT_FROM_OFF 0 |
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#define ATMEL_SAMA5_BOOT_FROM_MASK 0xf |
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#define ATMEL_SAMA5_BOOT_FROM_SPI (0 << 0) |
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#define ATMEL_SAMA5_BOOT_FROM_MCI (1 << 0) |
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#define ATMEL_SAMA5_BOOT_FROM_SMC (2 << 0) |
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#define ATMEL_SAMA5_BOOT_FROM_TWI (3 << 0) |
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#define ATMEL_SAMA5_BOOT_FROM_QSPI (4 << 0) |
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#define ATMEL_SAMA5_BOOT_FROM_SAMBA (7 << 0) |
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#define ATMEL_SAMA5_BOOT_DEV_ID_OFF 4 |
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#define ATMEL_SAMA5_BOOT_DEV_ID_MASK 0xf |
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#endif /* __SAMA5_BOOT_H */ |
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@ -0,0 +1,12 @@ |
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if TARGET_GURNARD |
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config SYS_BOARD |
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default "gurnard" |
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config SYS_VENDOR |
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default "bluewater" |
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config SYS_CONFIG_NAME |
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default "snapper9g45" |
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endif |
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@ -0,0 +1,6 @@ |
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GURNARD BOARD |
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M: Simon Glass <sjg@chromium.org> |
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S: Maintained |
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F: board/bluewater/gurnard/ |
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F: include/configs/snapper9g45.h |
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F: configs/gurnard_defconfig |
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@ -0,0 +1,11 @@ |
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2011 Bluewater Systems
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# Ryan Mallon <ryan@bluewatersys.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += gurnard.o
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@ -0,0 +1,449 @@ |
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/*
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* Bluewater Systems Snapper 9260/9G20 modules |
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* |
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* (C) Copyright 2011 Bluewater Systems |
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* Author: Andre Renaud <andre@bluewatersys.com> |
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* Author: Ryan Mallon <ryan@bluewatersys.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <atmel_lcd.h> |
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#include <atmel_lcdc.h> |
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#include <atmel_mci.h> |
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#include <dm.h> |
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#include <lcd.h> |
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#include <net.h> |
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#ifndef CONFIG_DM_ETH |
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#include <netdev.h> |
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#endif |
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#include <spi.h> |
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#include <asm/gpio.h> |
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#include <asm/io.h> |
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#include <asm/arch/at91sam9g45_matrix.h> |
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#include <asm/arch/at91sam9_smc.h> |
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#include <asm/arch/at91_common.h> |
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#include <asm/arch/at91_emac.h> |
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#include <asm/arch/at91_rstc.h> |
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#include <asm/arch/at91_rtc.h> |
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#include <asm/arch/at91_sck.h> |
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#include <asm/arch/atmel_serial.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/gpio.h> |
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#include <dm/uclass-internal.h> |
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#ifdef CONFIG_GURNARD_SPLASH |
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#include "splash_logo.h" |
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#endif |
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DECLARE_GLOBAL_DATA_PTR; |
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|
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/* IO Expander pins */ |
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#define IO_EXP_ETH_RESET (0 << 1) |
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#define IO_EXP_ETH_POWER (1 << 1) |
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|
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#ifdef CONFIG_MACB |
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static void gurnard_macb_hw_init(void) |
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{ |
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struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; |
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at91_periph_clk_enable(ATMEL_ID_EMAC); |
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/*
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* Enable pull-up on: |
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* RXDV (PA12) => MODE0 - PHY also has pull-up |
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* ERX0 (PA13) => MODE1 - PHY also has pull-up |
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* ERX1 (PA15) => MODE2 - PHY also has pull-up |
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*/ |
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writel(pin_to_mask(AT91_PIN_PA15) | |
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pin_to_mask(AT91_PIN_PA12) | |
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pin_to_mask(AT91_PIN_PA13), |
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&pioa->puer); |
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at91_phy_reset(); |
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at91_macb_hw_init(); |
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} |
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#endif |
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|
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#ifdef CONFIG_CMD_NAND |
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static int gurnard_nand_hw_init(void) |
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{ |
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; |
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; |
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ulong flags; |
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int ret; |
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|
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/* Enable CS3 as NAND/SmartMedia */ |
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setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); |
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|
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/* Configure SMC CS3 for NAND/SmartMedia */ |
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), |
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&smc->cs[3].setup); |
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), |
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&smc->cs[3].pulse); |
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writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), |
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&smc->cs[3].cycle); |
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#ifdef CONFIG_SYS_NAND_DBW_16 |
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flags = AT91_SMC_MODE_DBW_16; |
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#else |
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flags = AT91_SMC_MODE_DBW_8; |
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#endif |
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | |
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AT91_SMC_MODE_EXNW_DISABLE | |
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flags | |
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AT91_SMC_MODE_TDF_CYCLE(3), |
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&smc->cs[3].mode); |
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|
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ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy"); |
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if (ret) |
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return ret; |
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); |
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|
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/* Enable NandFlash */ |
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ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce"); |
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if (ret) |
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return ret; |
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); |
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|
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return 0; |
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} |
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#endif |
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|
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#ifdef CONFIG_GURNARD_SPLASH |
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static void lcd_splash(int width, int height) |
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{ |
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u16 colour; |
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int x, y; |
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u16 *base_addr = (u16 *)gd->video_bottom; |
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|
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memset(base_addr, 0xff, width * height * 2); |
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/*
|
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* Blit the logo to the center of the screen |
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*/ |
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for (y = 0; y < BMP_LOGO_HEIGHT; y++) { |
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for (x = 0; x < BMP_LOGO_WIDTH; x++) { |
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int posx, posy; |
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colour = bmp_logo_palette[bmp_logo_bitmap[ |
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y * BMP_LOGO_WIDTH + x]]; |
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posx = x + (width - BMP_LOGO_WIDTH) / 2; |
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posy = y; |
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base_addr[posy * width + posx] = colour; |
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} |
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} |
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} |
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#endif |
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|
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#ifdef CONFIG_DM_VIDEO |
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static void at91sam9g45_lcd_hw_init(void) |
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{ |
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at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ |
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at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ |
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at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ |
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at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ |
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at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ |
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|
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at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ |
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at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ |
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at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ |
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at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ |
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at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ |
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at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ |
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at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ |
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at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ |
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at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ |
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at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ |
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at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ |
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at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ |
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at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ |
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at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ |
||||
at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ |
||||
at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ |
||||
at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ |
||||
at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ |
||||
at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ |
||||
at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ |
||||
at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ |
||||
at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ |
||||
at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ |
||||
at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ |
||||
|
||||
at91_periph_clk_enable(ATMEL_ID_LCDC); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_GURNARD_FPGA |
||||
/**
|
||||
* Initialise the memory bus settings so that we can talk to the |
||||
* memory mapped FPGA |
||||
*/ |
||||
static int fpga_hw_init(void) |
||||
{ |
||||
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; |
||||
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; |
||||
int i; |
||||
|
||||
setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC); |
||||
|
||||
at91_set_a_periph(2, 4, 0); /* EBIA21 */ |
||||
at91_set_a_periph(2, 5, 0); /* EBIA22 */ |
||||
at91_set_a_periph(2, 6, 0); /* EBIA23 */ |
||||
at91_set_a_periph(2, 7, 0); /* EBIA24 */ |
||||
at91_set_a_periph(2, 12, 0); /* EBIA25 */ |
||||
for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */ |
||||
at91_set_a_periph(2, i, 0); |
||||
|
||||
/* configure SMC cs0 for FPGA access timing */ |
||||
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) | |
||||
AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2), |
||||
&smc->cs[0].setup); |
||||
writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) | |
||||
AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4), |
||||
&smc->cs[0].pulse); |
||||
writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), |
||||
&smc->cs[0].cycle); |
||||
writel(AT91_SMC_MODE_BAT | |
||||
AT91_SMC_MODE_EXNW_DISABLE | |
||||
AT91_SMC_MODE_DBW_32 | |
||||
AT91_SMC_MODE_TDF | |
||||
AT91_SMC_MODE_TDF_CYCLE(2), |
||||
&smc->cs[0].mode); |
||||
|
||||
/* Do a write to within EBI_CS1 to enable the SDCK */ |
||||
writel(0, ATMEL_BASE_CS1); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_USB |
||||
|
||||
#define USB0_ENABLE_PIN AT91_PIN_PB22 |
||||
#define USB1_ENABLE_PIN AT91_PIN_PB23 |
||||
|
||||
void gurnard_usb_init(void) |
||||
{ |
||||
at91_set_gpio_output(USB0_ENABLE_PIN, 1); |
||||
at91_set_gpio_value(USB0_ENABLE_PIN, 0); |
||||
at91_set_gpio_output(USB1_ENABLE_PIN, 1); |
||||
at91_set_gpio_value(USB1_ENABLE_PIN, 0); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_GENERIC_ATMEL_MCI |
||||
int cpu_mmc_init(bd_t *bis) |
||||
{ |
||||
return atmel_mci_init((void *)ATMEL_BASE_MCI0); |
||||
} |
||||
#endif |
||||
|
||||
static void gurnard_enable_console(int enable) |
||||
{ |
||||
at91_set_gpio_output(AT91_PIN_PB14, 1); |
||||
at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1); |
||||
} |
||||
|
||||
void at91sam9g45_slowclock_init(void) |
||||
{ |
||||
/*
|
||||
* On AT91SAM9G45 revC CPUs, the slow clock can be based on an |
||||
* internal impreciseRC oscillator or an external 32kHz oscillator. |
||||
* Switch to the latter. |
||||
*/ |
||||
unsigned i, tmp; |
||||
ulong *reg = (ulong *)ATMEL_BASE_SCKCR; |
||||
|
||||
tmp = readl(reg); |
||||
if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) { |
||||
timer_init(); |
||||
tmp |= AT91SAM9G45_SCKCR_OSC32EN; |
||||
writel(tmp, reg); |
||||
for (i = 0; i < 1200; i++) |
||||
udelay(1000); |
||||
tmp |= AT91SAM9G45_SCKCR_OSCSEL_32; |
||||
writel(tmp, reg); |
||||
udelay(200); |
||||
tmp &= ~AT91SAM9G45_SCKCR_RCEN; |
||||
writel(tmp, reg); |
||||
} |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
at91_seriald_hw_init(); |
||||
gurnard_enable_console(1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
const char *rev_str; |
||||
#ifdef CONFIG_CMD_NAND |
||||
int ret; |
||||
#endif |
||||
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOA); |
||||
at91_periph_clk_enable(ATMEL_ID_PIOB); |
||||
at91_periph_clk_enable(ATMEL_ID_PIOC); |
||||
at91_periph_clk_enable(ATMEL_ID_PIODE); |
||||
|
||||
at91sam9g45_slowclock_init(); |
||||
|
||||
/*
|
||||
* Clear the RTC IDR to disable all IRQs. Avoid issues when Linux |
||||
* boots with spurious IRQs. |
||||
*/ |
||||
writel(0xffffffff, AT91_RTC_IDR); |
||||
|
||||
/* Make sure that the reset signal is attached properly */ |
||||
setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN); |
||||
|
||||
gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260; |
||||
|
||||
/* Address of boot parameters */ |
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
||||
|
||||
#ifdef CONFIG_CMD_NAND |
||||
ret = gurnard_nand_hw_init(); |
||||
if (ret) |
||||
return ret; |
||||
#endif |
||||
#ifdef CONFIG_ATMEL_SPI |
||||
at91_spi0_hw_init(1 << 4); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MACB |
||||
gurnard_macb_hw_init(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_GURNARD_FPGA |
||||
fpga_hw_init(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_USB |
||||
gurnard_usb_init(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_MMC |
||||
at91_set_A_periph(AT91_PIN_PA12, 0); |
||||
at91_set_gpio_output(AT91_PIN_PA8, 1); |
||||
at91_set_gpio_value(AT91_PIN_PA8, 0); |
||||
at91_mci_hw_init(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_DM_VIDEO |
||||
at91sam9g45_lcd_hw_init(); |
||||
at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ |
||||
|
||||
/* Select the second timing index for board rev 2 */ |
||||
rev_str = getenv("board_rev"); |
||||
if (rev_str && !strncmp(rev_str, "2", 1)) { |
||||
struct udevice *dev; |
||||
|
||||
uclass_find_first_device(UCLASS_VIDEO, &dev); |
||||
if (dev) { |
||||
struct atmel_lcd_platdata *plat = dev_get_platdata(dev); |
||||
|
||||
plat->timing_index = 1; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
u_int8_t env_enetaddr[8]; |
||||
char *env_str; |
||||
char *end; |
||||
int i; |
||||
|
||||
/*
|
||||
* Set MAC address so we do not need to init Ethernet before Linux |
||||
* boot |
||||
*/ |
||||
env_str = getenv("ethaddr"); |
||||
if (env_str) { |
||||
struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC; |
||||
/* Parse MAC address */ |
||||
for (i = 0; i < 6; i++) { |
||||
env_enetaddr[i] = env_str ? |
||||
simple_strtoul(env_str, &end, 16) : 0; |
||||
if (env_str) |
||||
env_str = (*end) ? end+1 : end; |
||||
} |
||||
|
||||
/* Set hardware address */ |
||||
writel(env_enetaddr[0] | env_enetaddr[1] << 8 | |
||||
env_enetaddr[2] << 16 | env_enetaddr[3] << 24, |
||||
&emac->sa2l); |
||||
writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h); |
||||
|
||||
printf("MAC: %s\n", getenv("ethaddr")); |
||||
} else { |
||||
/* Not set in environment */ |
||||
printf("MAC: not set\n"); |
||||
} |
||||
#ifdef CONFIG_GURNARD_SPLASH |
||||
lcd_splash(480, 272); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifndef CONFIG_DM_ETH |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0); |
||||
} |
||||
#endif |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
||||
CONFIG_SYS_SDRAM_SIZE); |
||||
return 0; |
||||
} |
||||
|
||||
void reset_phy(void) |
||||
{ |
||||
} |
||||
|
||||
/* This breaks the Ethernet MAC at present */ |
||||
void enable_caches(void) |
||||
{ |
||||
dcache_enable(); |
||||
} |
||||
|
||||
/* SPI chip select control - only used for FPGA programming */ |
||||
#ifdef CONFIG_ATMEL_SPI |
||||
|
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
||||
{ |
||||
return bus == 0 && cs == 0; |
||||
} |
||||
|
||||
void spi_cs_activate(struct spi_slave *slave) |
||||
{ |
||||
/* We don't use chipselects for FPGA programming */ |
||||
} |
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave) |
||||
{ |
||||
/* We don't use chipselects for FPGA programming */ |
||||
} |
||||
#endif /* CONFIG_ATMEL_SPI */ |
||||
|
||||
static struct atmel_serial_platdata at91sam9260_serial_plat = { |
||||
.base_addr = ATMEL_BASE_DBGU, |
||||
}; |
||||
|
||||
U_BOOT_DEVICE(at91sam9260_serial) = { |
||||
.name = "serial_atmel", |
||||
.platdata = &at91sam9260_serial_plat, |
||||
}; |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,20 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_AT91=y |
||||
CONFIG_TARGET_GURNARD=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard" |
||||
CONFIG_FIT=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" |
||||
CONFIG_BOOTDELAY=3 |
||||
# CONFIG_CMD_BDI is not set |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_LOADS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
||||
# CONFIG_CMD_SOURCE is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM_VIDEO=y |
||||
CONFIG_CMD_DHRYSTONE=y |
||||
# CONFIG_EFI_LOADER is not set |
||||
@ -0,0 +1,155 @@ |
||||
/*
|
||||
* Bluewater Systems Snapper 9G45 module |
||||
* |
||||
* (C) Copyright 2011 Bluewater Systems |
||||
* Author: Andre Renaud <andre@bluewatersys.com> |
||||
* Author: Ryan Mallon <ryan@bluewatersys.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* SoC type is defined in boards.cfg */ |
||||
#include <asm/hardware.h> |
||||
#include <linux/sizes.h> |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x73f00000 |
||||
|
||||
/* ARM asynchronous clock */ |
||||
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ |
||||
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
||||
|
||||
/* CPU */ |
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
/* SDRAM */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 |
||||
#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ |
||||
#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/* Mem test settings */ |
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) |
||||
|
||||
/* NAND Flash */ |
||||
#define CONFIG_NAND_ATMEL |
||||
#define CONFIG_ATMEL_NAND_HWECC |
||||
#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
||||
#define CONFIG_SYS_NAND_DBW_8 |
||||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ |
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ |
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 |
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 |
||||
|
||||
/* Ethernet */ |
||||
#define CONFIG_MACB |
||||
#define CONFIG_RMII |
||||
#define CONFIG_NET_RETRY_COUNT 20 |
||||
#define CONFIG_RESET_PHY_R |
||||
#define CONFIG_AT91_WANTS_COMMON_PHY |
||||
#define CONFIG_TFTP_PORT |
||||
#define CONFIG_TFTP_TSIZE |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_ATMEL |
||||
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_PARTITION_UUIDS |
||||
|
||||
/* MMC */ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_GENERIC_ATMEL_MCI |
||||
|
||||
/* LCD */ |
||||
#define CONFIG_ATMEL_LCD |
||||
#define CONFIG_CONSOLE_MUX |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
#define CONFIG_GURNARD_SPLASH |
||||
|
||||
#define CONFIG_ATMEL_SPI |
||||
|
||||
/* GPIOs and IO expander */ |
||||
#define CONFIG_ATMEL_LEGACY |
||||
#define CONFIG_AT91_GPIO |
||||
#define CONFIG_AT91_GPIO_PULLUP 1 |
||||
|
||||
/* UARTs/Serial console */ |
||||
#define CONFIG_ATMEL_USART |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* Boot options */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x23000000 |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK |
||||
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/* Environment settings */ |
||||
#define CONFIG_ENV_IS_IN_NAND |
||||
#define CONFIG_ENV_OFFSET (512 << 10) |
||||
#define CONFIG_ENV_SIZE (256 << 10) |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"ethaddr=00:00:00:00:00:00\0" \
|
||||
"serial=0\0" \
|
||||
"stdout=serial_atmel\0" \
|
||||
"stderr=serial_atmel\0" \
|
||||
"stdin=serial_atmel\0" \
|
||||
"bootlimit=3\0" \
|
||||
"loadaddr=0x71000000\0" \
|
||||
"board_rev=2\0" \
|
||||
"bootfile=/tftpboot/uImage\0" \
|
||||
"bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \
|
||||
"nfsroot=/export/root\0" \
|
||||
"boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \
|
||||
"boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \
|
||||
"boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \
|
||||
"boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \
|
||||
"boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \
|
||||
"bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \
|
||||
"altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0" |
||||
|
||||
/* Console settings */ |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
/* U-Boot memory settings */ |
||||
#define CONFIG_SYS_MALLOC_LEN (1 << 20) |
||||
|
||||
/* Command line configuration */ |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_PART |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,23 @@ |
||||
/*
|
||||
* This header provides constants for AT91 pmc status. |
||||
* |
||||
* The constants defined in this header are being used in dts. |
||||
* |
||||
* Licensed under GPLv2 or later. |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_CLK_AT91_H |
||||
#define _DT_BINDINGS_CLK_AT91_H |
||||
|
||||
#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ |
||||
#define AT91_PMC_LOCKA 1 /* PLLA Lock */ |
||||
#define AT91_PMC_LOCKB 2 /* PLLB Lock */ |
||||
#define AT91_PMC_MCKRDY 3 /* Master Clock */ |
||||
#define AT91_PMC_LOCKU 6 /* UPLL Lock */ |
||||
#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ |
||||
#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ |
||||
#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ |
||||
#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ |
||||
#define AT91_PMC_GCKRDY 24 /* Generated Clocks */ |
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|
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#endif |
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@ -0,0 +1,52 @@ |
||||
/*
|
||||
* This header provides macros for at91 dma bindings. |
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* |
||||
* Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com> |
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* |
||||
* GPLv2 only |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_AT91_DMA_H__ |
||||
#define __DT_BINDINGS_AT91_DMA_H__ |
||||
|
||||
/* ---------- HDMAC ---------- */ |
||||
|
||||
/*
|
||||
* Source and/or destination peripheral ID |
||||
*/ |
||||
#define AT91_DMA_CFG_PER_ID_MASK (0xff) |
||||
#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) |
||||
|
||||
/*
|
||||
* FIFO configuration: it defines when a request is serviced. |
||||
*/ |
||||
#define AT91_DMA_CFG_FIFOCFG_OFFSET (8) |
||||
#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) |
||||
#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ |
||||
#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ |
||||
#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ |
||||
|
||||
|
||||
/* ---------- XDMAC ---------- */ |
||||
#define AT91_XDMAC_DT_MEM_IF_MASK (0x1) |
||||
#define AT91_XDMAC_DT_MEM_IF_OFFSET (13) |
||||
#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ |
||||
<< AT91_XDMAC_DT_MEM_IF_OFFSET) |
||||
#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ |
||||
& AT91_XDMAC_DT_MEM_IF_MASK) |
||||
|
||||
#define AT91_XDMAC_DT_PER_IF_MASK (0x1) |
||||
#define AT91_XDMAC_DT_PER_IF_OFFSET (14) |
||||
#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ |
||||
<< AT91_XDMAC_DT_PER_IF_OFFSET) |
||||
#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ |
||||
& AT91_XDMAC_DT_PER_IF_MASK) |
||||
|
||||
#define AT91_XDMAC_DT_PERID_MASK (0x7f) |
||||
#define AT91_XDMAC_DT_PERID_OFFSET (24) |
||||
#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ |
||||
<< AT91_XDMAC_DT_PERID_OFFSET) |
||||
#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ |
||||
& AT91_XDMAC_DT_PERID_MASK) |
||||
|
||||
#endif /* __DT_BINDINGS_AT91_DMA_H__ */ |
||||
@ -0,0 +1,40 @@ |
||||
/*
|
||||
* This header provides constants for most at91 pinctrl bindings. |
||||
* |
||||
* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
||||
* |
||||
* GPLv2 only |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_AT91_PINCTRL_H__ |
||||
#define __DT_BINDINGS_AT91_PINCTRL_H__ |
||||
|
||||
#define AT91_PINCTRL_NONE (0 << 0) |
||||
#define AT91_PINCTRL_PULL_UP (1 << 0) |
||||
#define AT91_PINCTRL_MULTI_DRIVE (1 << 1) |
||||
#define AT91_PINCTRL_DEGLITCH (1 << 2) |
||||
#define AT91_PINCTRL_PULL_DOWN (1 << 3) |
||||
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4) |
||||
#define AT91_PINCTRL_DEBOUNCE (1 << 16) |
||||
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17) |
||||
|
||||
#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) |
||||
|
||||
#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5) |
||||
#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5) |
||||
#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) |
||||
#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) |
||||
|
||||
#define AT91_PIOA 0 |
||||
#define AT91_PIOB 1 |
||||
#define AT91_PIOC 2 |
||||
#define AT91_PIOD 3 |
||||
#define AT91_PIOE 4 |
||||
|
||||
#define AT91_PERIPH_GPIO 0 |
||||
#define AT91_PERIPH_A 1 |
||||
#define AT91_PERIPH_B 2 |
||||
#define AT91_PERIPH_C 3 |
||||
#define AT91_PERIPH_D 4 |
||||
|
||||
#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ |
||||
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Reference in new issue