Tom Rini
7 years ago
commit
fdb6c3232f
@ -0,0 +1,768 @@ |
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/*
|
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* Copyright (C) 2017 |
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* Broadcom |
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* Florian Fainelli <f.fainelli@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/*
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* PHY driver for Broadcom BCM53xx (roboswitch) Ethernet switches. |
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* |
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* This driver configures the b53 for basic use as a PHY. The switch supports |
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* vendor tags and VLAN configuration that can affect the switching decisions. |
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* This driver uses a simple configuration in which all ports are only allowed |
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* to send frames to the CPU port and receive frames from the CPU port this |
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* providing port isolation (no cross talk). |
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* |
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* The configuration determines which PHY ports to activate using the |
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* CONFIG_B53_PHY_PORTS bitmask. Set bit N will active port N and so on. |
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* |
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* This driver was written primarily for the Lamobo R1 platform using a BCM53152 |
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* switch but the BCM53xx being largely register compatible, extending it to |
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* cover other switches would be trivial. |
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*/ |
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#include <common.h> |
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#include <errno.h> |
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#include <malloc.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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/* Pseudo-PHY address (non configurable) to access internal registers */ |
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#define BRCM_PSEUDO_PHY_ADDR 30 |
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/* Maximum number of ports possible */ |
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#define B53_N_PORTS 9 |
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#define B53_CTRL_PAGE 0x00 /* Control */ |
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#define B53_MGMT_PAGE 0x02 /* Management Mode */ |
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/* Port VLAN Page */ |
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#define B53_PVLAN_PAGE 0x31 |
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/* Control Page registers */ |
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#define B53_PORT_CTRL(i) (0x00 + (i)) |
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#define PORT_CTRL_RX_DISABLE BIT(0) |
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#define PORT_CTRL_TX_DISABLE BIT(1) |
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#define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ |
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#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ |
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#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ |
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/* Switch Mode Control Register (8 bit) */ |
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#define B53_SWITCH_MODE 0x0b |
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#define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */ |
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#define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */ |
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/* IMP Port state override register (8 bit) */ |
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#define B53_PORT_OVERRIDE_CTRL 0x0e |
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#define PORT_OVERRIDE_LINK BIT(0) |
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#define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ |
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#define PORT_OVERRIDE_SPEED_S 2 |
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#define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S) |
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#define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S) |
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#define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S) |
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/* BCM5325 only */ |
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#define PORT_OVERRIDE_RV_MII_25 BIT(4) |
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#define PORT_OVERRIDE_RX_FLOW BIT(4) |
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#define PORT_OVERRIDE_TX_FLOW BIT(5) |
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/* BCM5301X only, requires setting 1000M */ |
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#define PORT_OVERRIDE_SPEED_2000M BIT(6) |
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#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */ |
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#define B53_RGMII_CTRL_IMP 0x60 |
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#define RGMII_CTRL_ENABLE_GMII BIT(7) |
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#define RGMII_CTRL_TIMING_SEL BIT(2) |
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#define RGMII_CTRL_DLL_RXC BIT(1) |
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#define RGMII_CTRL_DLL_TXC BIT(0) |
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/* Switch control (8 bit) */ |
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#define B53_SWITCH_CTRL 0x22 |
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#define B53_MII_DUMB_FWDG_EN BIT(6) |
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/* Software reset register (8 bit) */ |
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#define B53_SOFTRESET 0x79 |
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#define SW_RST BIT(7) |
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#define EN_CH_RST BIT(6) |
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#define EN_SW_RST BIT(4) |
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/* Fast Aging Control register (8 bit) */ |
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#define B53_FAST_AGE_CTRL 0x88 |
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#define FAST_AGE_STATIC BIT(0) |
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#define FAST_AGE_DYNAMIC BIT(1) |
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#define FAST_AGE_PORT BIT(2) |
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#define FAST_AGE_VLAN BIT(3) |
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#define FAST_AGE_STP BIT(4) |
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#define FAST_AGE_MC BIT(5) |
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#define FAST_AGE_DONE BIT(7) |
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/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ |
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#define B53_PVLAN_PORT_MASK(i) ((i) * 2) |
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/* MII registers */ |
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#define REG_MII_PAGE 0x10 /* MII Page register */ |
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#define REG_MII_ADDR 0x11 /* MII Address register */ |
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#define REG_MII_DATA0 0x18 /* MII Data register 0 */ |
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#define REG_MII_DATA1 0x19 /* MII Data register 1 */ |
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#define REG_MII_DATA2 0x1a /* MII Data register 2 */ |
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#define REG_MII_DATA3 0x1b /* MII Data register 3 */ |
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#define REG_MII_PAGE_ENABLE BIT(0) |
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#define REG_MII_ADDR_WRITE BIT(0) |
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#define REG_MII_ADDR_READ BIT(1) |
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struct b53_device { |
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struct mii_dev *bus; |
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unsigned int cpu_port; |
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}; |
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static int b53_mdio_op(struct mii_dev *bus, u8 page, u8 reg, u16 op) |
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{ |
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int ret; |
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int i; |
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u16 v; |
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/* set page number */ |
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v = (page << 8) | REG_MII_PAGE_ENABLE; |
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ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_PAGE, v); |
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if (ret) |
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return ret; |
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|
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/* set register address */ |
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v = (reg << 8) | op; |
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ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_ADDR, v); |
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if (ret) |
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return ret; |
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/* check if operation completed */ |
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for (i = 0; i < 5; ++i) { |
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v = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_ADDR); |
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if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ))) |
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break; |
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udelay(100); |
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} |
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if (i == 5) |
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return -EIO; |
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return 0; |
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} |
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static int b53_mdio_read8(struct mii_dev *bus, u8 page, u8 reg, u8 *val) |
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{ |
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int ret; |
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ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ); |
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if (ret) |
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return ret; |
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*val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_DATA0) & 0xff; |
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return 0; |
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} |
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static int b53_mdio_read16(struct mii_dev *bus, u8 page, u8 reg, u16 *val) |
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{ |
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int ret; |
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ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ); |
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if (ret) |
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return ret; |
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*val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_DATA0); |
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return 0; |
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} |
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static int b53_mdio_read32(struct mii_dev *bus, u8 page, u8 reg, u32 *val) |
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{ |
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int ret; |
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ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ); |
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if (ret) |
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return ret; |
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*val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_DATA0); |
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*val |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_DATA1) << 16; |
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return 0; |
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} |
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static int b53_mdio_read48(struct mii_dev *bus, u8 page, u8 reg, u64 *val) |
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{ |
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u64 temp = 0; |
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int i; |
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int ret; |
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ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ); |
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if (ret) |
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return ret; |
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for (i = 2; i >= 0; i--) { |
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temp <<= 16; |
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temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_DATA0 + i); |
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} |
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*val = temp; |
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return 0; |
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} |
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static int b53_mdio_read64(struct mii_dev *bus, u8 page, u8 reg, u64 *val) |
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{ |
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u64 temp = 0; |
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int i; |
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int ret; |
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ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ); |
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if (ret) |
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return ret; |
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for (i = 3; i >= 0; i--) { |
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temp <<= 16; |
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temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_DATA0 + i); |
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} |
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*val = temp; |
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return 0; |
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} |
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static int b53_mdio_write8(struct mii_dev *bus, u8 page, u8 reg, u8 value) |
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{ |
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int ret; |
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ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_DATA0, value); |
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if (ret) |
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return ret; |
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return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE); |
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} |
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static int b53_mdio_write16(struct mii_dev *bus, u8 page, u8 reg, |
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u16 value) |
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{ |
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int ret; |
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ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, |
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REG_MII_DATA0, value); |
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if (ret) |
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return ret; |
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return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE); |
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} |
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static int b53_mdio_write32(struct mii_dev *bus, u8 page, u8 reg, |
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u32 value) |
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{ |
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unsigned int i; |
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u32 temp = value; |
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for (i = 0; i < 2; i++) { |
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int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, |
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MDIO_DEVAD_NONE, |
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REG_MII_DATA0 + i, temp & 0xffff); |
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if (ret) |
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return ret; |
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temp >>= 16; |
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} |
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return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE); |
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} |
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static int b53_mdio_write48(struct mii_dev *bus, u8 page, u8 reg, |
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u64 value) |
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{ |
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unsigned int i; |
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u64 temp = value; |
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for (i = 0; i < 3; i++) { |
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int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, |
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MDIO_DEVAD_NONE, |
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REG_MII_DATA0 + i, temp & 0xffff); |
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if (ret) |
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return ret; |
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temp >>= 16; |
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} |
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return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE); |
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} |
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static int b53_mdio_write64(struct mii_dev *bus, u8 page, u8 reg, |
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u64 value) |
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{ |
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unsigned int i; |
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u64 temp = value; |
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for (i = 0; i < 4; i++) { |
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int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, |
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MDIO_DEVAD_NONE, |
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REG_MII_DATA0 + i, temp & 0xffff); |
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if (ret) |
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return ret; |
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temp >>= 16; |
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} |
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return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE); |
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} |
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static inline int b53_read8(struct b53_device *dev, u8 page, |
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u8 reg, u8 *value) |
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{ |
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return b53_mdio_read8(dev->bus, page, reg, value); |
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} |
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static inline int b53_read16(struct b53_device *dev, u8 page, |
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u8 reg, u16 *value) |
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{ |
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return b53_mdio_read16(dev->bus, page, reg, value); |
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} |
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static inline int b53_read32(struct b53_device *dev, u8 page, |
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u8 reg, u32 *value) |
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{ |
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return b53_mdio_read32(dev->bus, page, reg, value); |
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} |
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static inline int b53_read48(struct b53_device *dev, u8 page, |
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u8 reg, u64 *value) |
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{ |
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return b53_mdio_read48(dev->bus, page, reg, value); |
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} |
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static inline int b53_read64(struct b53_device *dev, u8 page, |
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u8 reg, u64 *value) |
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{ |
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return b53_mdio_read64(dev->bus, page, reg, value); |
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} |
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static inline int b53_write8(struct b53_device *dev, u8 page, |
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u8 reg, u8 value) |
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{ |
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return b53_mdio_write8(dev->bus, page, reg, value); |
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} |
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static inline int b53_write16(struct b53_device *dev, u8 page, |
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u8 reg, u16 value) |
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{ |
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return b53_mdio_write16(dev->bus, page, reg, value); |
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} |
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static inline int b53_write32(struct b53_device *dev, u8 page, |
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u8 reg, u32 value) |
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{ |
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return b53_mdio_write32(dev->bus, page, reg, value); |
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} |
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static inline int b53_write48(struct b53_device *dev, u8 page, |
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u8 reg, u64 value) |
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{ |
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return b53_mdio_write48(dev->bus, page, reg, value); |
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} |
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static inline int b53_write64(struct b53_device *dev, u8 page, |
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u8 reg, u64 value) |
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{ |
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return b53_mdio_write64(dev->bus, page, reg, value); |
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} |
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static int b53_flush_arl(struct b53_device *dev, u8 mask) |
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{ |
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unsigned int i; |
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b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, |
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FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); |
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for (i = 0; i < 10; i++) { |
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u8 fast_age_ctrl; |
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b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, |
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&fast_age_ctrl); |
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if (!(fast_age_ctrl & FAST_AGE_DONE)) |
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goto out; |
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mdelay(1); |
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} |
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return -ETIMEDOUT; |
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out: |
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/* Only age dynamic entries (default behavior) */ |
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b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); |
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return 0; |
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} |
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static int b53_switch_reset(struct phy_device *phydev) |
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{ |
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struct b53_device *dev = phydev->priv; |
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unsigned int timeout = 1000; |
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u8 mgmt; |
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u8 reg; |
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b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); |
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reg |= SW_RST | EN_SW_RST | EN_CH_RST; |
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b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); |
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do { |
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b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); |
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if (!(reg & SW_RST)) |
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break; |
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mdelay(1); |
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} while (timeout-- > 0); |
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if (timeout == 0) |
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return -ETIMEDOUT; |
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b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); |
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if (!(mgmt & SM_SW_FWD_EN)) { |
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mgmt &= ~SM_SW_FWD_MODE; |
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mgmt |= SM_SW_FWD_EN; |
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b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); |
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b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); |
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if (!(mgmt & SM_SW_FWD_EN)) { |
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printf("Failed to enable switch!\n"); |
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return -EINVAL; |
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} |
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} |
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/* Include IMP port in dumb forwarding mode when no tagging protocol
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* is configured |
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*/ |
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b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); |
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mgmt |= B53_MII_DUMB_FWDG_EN; |
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b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); |
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return b53_flush_arl(dev, FAST_AGE_STATIC); |
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} |
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static void b53_enable_cpu_port(struct phy_device *phydev) |
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{ |
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struct b53_device *dev = phydev->priv; |
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u8 port_ctrl; |
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|
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port_ctrl = PORT_CTRL_RX_BCST_EN | |
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PORT_CTRL_RX_MCST_EN | |
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PORT_CTRL_RX_UCST_EN; |
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b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(dev->cpu_port), port_ctrl); |
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|
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port_ctrl = PORT_OVERRIDE_EN | PORT_OVERRIDE_LINK | |
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PORT_OVERRIDE_FULL_DUPLEX | PORT_OVERRIDE_SPEED_1000M; |
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b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, port_ctrl); |
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|
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b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_IMP, &port_ctrl); |
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} |
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|
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static void b53_imp_vlan_setup(struct b53_device *dev, int cpu_port) |
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{ |
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unsigned int port; |
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u16 pvlan; |
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|
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/* Enable the IMP port to be in the same VLAN as the other ports
|
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* on a per-port basis such that we only have Port i and IMP in |
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* the same VLAN. |
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*/ |
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for (port = 0; port < B53_N_PORTS; port++) { |
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if (!((1 << port) & CONFIG_B53_PHY_PORTS)) |
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continue; |
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|
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b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), |
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&pvlan); |
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pvlan |= BIT(cpu_port); |
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b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), |
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pvlan); |
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} |
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} |
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|
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static int b53_port_enable(struct phy_device *phydev, unsigned int port) |
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{ |
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struct b53_device *dev = phydev->priv; |
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unsigned int cpu_port = dev->cpu_port; |
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u16 pvlan; |
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|
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/* Clear the Rx and Tx disable bits and set to no spanning tree */ |
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b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); |
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|
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/* Set this port, and only this one to be in the default VLAN */ |
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b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); |
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pvlan &= ~0x1ff; |
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pvlan |= BIT(port); |
||||
b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); |
||||
|
||||
b53_imp_vlan_setup(dev, cpu_port); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int b53_switch_init(struct phy_device *phydev) |
||||
{ |
||||
static int init; |
||||
int ret; |
||||
|
||||
if (init) |
||||
return 0; |
||||
|
||||
ret = b53_switch_reset(phydev); |
||||
if (ret < 0) |
||||
return ret; |
||||
|
||||
b53_enable_cpu_port(phydev); |
||||
|
||||
init = 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int b53_probe(struct phy_device *phydev) |
||||
{ |
||||
struct b53_device *dev; |
||||
int ret; |
||||
|
||||
dev = malloc(sizeof(*dev)); |
||||
if (!dev) |
||||
return -ENOMEM; |
||||
|
||||
memset(dev, 0, sizeof(*dev)); |
||||
|
||||
phydev->priv = dev; |
||||
dev->bus = phydev->bus; |
||||
dev->cpu_port = CONFIG_B53_CPU_PORT; |
||||
|
||||
ret = b53_switch_reset(phydev); |
||||
if (ret < 0) |
||||
return ret; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int b53_phy_config(struct phy_device *phydev) |
||||
{ |
||||
unsigned int port; |
||||
int res; |
||||
|
||||
res = b53_switch_init(phydev); |
||||
if (res < 0) |
||||
return res; |
||||
|
||||
for (port = 0; port < B53_N_PORTS; port++) { |
||||
if (!((1 << port) & CONFIG_B53_PHY_PORTS)) |
||||
continue; |
||||
|
||||
res = b53_port_enable(phydev, port); |
||||
if (res < 0) { |
||||
printf("Error enabling port %i\n", port); |
||||
continue; |
||||
} |
||||
|
||||
res = genphy_config_aneg(phydev); |
||||
if (res < 0) { |
||||
printf("Error setting PHY %i autoneg\n", port); |
||||
continue; |
||||
} |
||||
|
||||
res = 0; |
||||
} |
||||
|
||||
return res; |
||||
} |
||||
|
||||
static int b53_phy_startup(struct phy_device *phydev) |
||||
{ |
||||
unsigned int port; |
||||
int res; |
||||
|
||||
for (port = 0; port < B53_N_PORTS; port++) { |
||||
if (!((1 << port) & CONFIG_B53_PHY_PORTS)) |
||||
continue; |
||||
|
||||
phydev->addr = port; |
||||
|
||||
res = genphy_startup(phydev); |
||||
if (res < 0) |
||||
continue; |
||||
else |
||||
break; |
||||
} |
||||
|
||||
/* Since we are connected directly to the switch, hardcode the link
|
||||
* parameters to match those of the CPU port configured in |
||||
* b53_enable_cpu_port, we cannot be dependent on the user-facing port |
||||
* settings (e.g: 100Mbits/sec would not work here) |
||||
*/ |
||||
phydev->speed = 1000; |
||||
phydev->duplex = 1; |
||||
phydev->link = 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct phy_driver b53_driver = { |
||||
.name = "Broadcom BCM53125", |
||||
.uid = 0x03625c00, |
||||
.mask = 0xfffffc00, |
||||
.features = PHY_GBIT_FEATURES, |
||||
.probe = b53_probe, |
||||
.config = b53_phy_config, |
||||
.startup = b53_phy_startup, |
||||
.shutdown = &genphy_shutdown, |
||||
}; |
||||
|
||||
int phy_b53_init(void) |
||||
{ |
||||
phy_register(&b53_driver); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int do_b53_reg_read(const char *name, int argc, char * const argv[]) |
||||
{ |
||||
u8 page, offset, width; |
||||
struct mii_dev *bus; |
||||
int ret = -EINVAL; |
||||
u64 value64 = 0; |
||||
u32 value32 = 0; |
||||
u16 value16 = 0; |
||||
u8 value8 = 0; |
||||
|
||||
bus = miiphy_get_dev_by_name(name); |
||||
if (!bus) { |
||||
printf("unable to find MDIO bus: %s\n", name); |
||||
return ret; |
||||
} |
||||
|
||||
page = simple_strtoul(argv[1], NULL, 16); |
||||
offset = simple_strtoul(argv[2], NULL, 16); |
||||
width = simple_strtoul(argv[3], NULL, 10); |
||||
|
||||
switch (width) { |
||||
case 8: |
||||
ret = b53_mdio_read8(bus, page, offset, &value8); |
||||
printf("page=0x%02x, offset=0x%02x, value=0x%02x\n", |
||||
page, offset, value8); |
||||
break; |
||||
case 16: |
||||
ret = b53_mdio_read16(bus, page, offset, &value16); |
||||
printf("page=0x%02x, offset=0x%02x, value=0x%04x\n", |
||||
page, offset, value16); |
||||
break; |
||||
case 32: |
||||
ret = b53_mdio_read32(bus, page, offset, &value32); |
||||
printf("page=0x%02x, offset=0x%02x, value=0x%08x\n", |
||||
page, offset, value32); |
||||
break; |
||||
case 48: |
||||
ret = b53_mdio_read48(bus, page, offset, &value64); |
||||
printf("page=0x%02x, offset=0x%02x, value=0x%012llx\n", |
||||
page, offset, value64); |
||||
break; |
||||
case 64: |
||||
ret = b53_mdio_read48(bus, page, offset, &value64); |
||||
printf("page=0x%02x, offset=0x%02x, value=0x%016llx\n", |
||||
page, offset, value64); |
||||
break; |
||||
default: |
||||
printf("Unsupported width: %d\n", width); |
||||
break; |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int do_b53_reg_write(const char *name, int argc, char * const argv[]) |
||||
{ |
||||
u8 page, offset, width; |
||||
struct mii_dev *bus; |
||||
int ret = -EINVAL; |
||||
u64 value64 = 0; |
||||
u32 value = 0; |
||||
|
||||
bus = miiphy_get_dev_by_name(name); |
||||
if (!bus) { |
||||
printf("unable to find MDIO bus: %s\n", name); |
||||
return ret; |
||||
} |
||||
|
||||
page = simple_strtoul(argv[1], NULL, 16); |
||||
offset = simple_strtoul(argv[2], NULL, 16); |
||||
width = simple_strtoul(argv[3], NULL, 10); |
||||
if (width == 48 || width == 64) |
||||
value64 = simple_strtoull(argv[4], NULL, 16); |
||||
else |
||||
value = simple_strtoul(argv[4], NULL, 16); |
||||
|
||||
switch (width) { |
||||
case 8: |
||||
ret = b53_mdio_write8(bus, page, offset, value & 0xff); |
||||
break; |
||||
case 16: |
||||
ret = b53_mdio_write16(bus, page, offset, value); |
||||
break; |
||||
case 32: |
||||
ret = b53_mdio_write32(bus, page, offset, value); |
||||
break; |
||||
case 48: |
||||
ret = b53_mdio_write48(bus, page, offset, value64); |
||||
break; |
||||
case 64: |
||||
ret = b53_mdio_write64(bus, page, offset, value64); |
||||
break; |
||||
default: |
||||
printf("Unsupported width: %d\n", width); |
||||
break; |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int do_b53_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
const char *cmd, *mdioname; |
||||
int ret = 0; |
||||
|
||||
if (argc < 2) |
||||
return cmd_usage(cmdtp); |
||||
|
||||
cmd = argv[1]; |
||||
--argc; |
||||
++argv; |
||||
|
||||
if (!strcmp(cmd, "write")) { |
||||
if (argc < 4) |
||||
return cmd_usage(cmdtp); |
||||
mdioname = argv[1]; |
||||
--argc; |
||||
++argv; |
||||
ret = do_b53_reg_write(mdioname, argc, argv); |
||||
} else if (!strcmp(cmd, "read")) { |
||||
if (argc < 5) |
||||
return cmd_usage(cmdtp); |
||||
mdioname = argv[1]; |
||||
--argc; |
||||
++argv; |
||||
ret = do_b53_reg_read(mdioname, argc, argv); |
||||
} else { |
||||
return cmd_usage(cmdtp); |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
U_BOOT_CMD(b53_reg, 7, 1, do_b53_reg, |
||||
"Broadcom B53 switch register access", |
||||
"write mdioname page (hex) offset (hex) width (dec) value (hex)\n" |
||||
"read mdioname page (hex) offset (hex) width (dec)\n" |
||||
); |
||||
Loading…
Reference in new issue