The patch adds support for P2020DS reference platform. DDR3 interface uses hard-coded initialization rather than SPD for now and was tested at 667Mhz. Some PIXIS register definitions and associated code sections need to be fixed. TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all tested under u-boot. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>master
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@ -0,0 +1,54 @@ |
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#
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# Copyright 2007-2009 Freescale Semiconductor, Inc.
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# (C) Copyright 2001-2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(OBJS) $(SOBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,32 @@ |
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#
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# Copyright 2007-2009 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# p2020ds board
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#
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ifndef TEXT_BASE |
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TEXT_BASE = 0xeff80000
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endif |
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PLATFORM_CPPFLAGS += -DCONFIG_E500=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_P2020=1
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@ -0,0 +1,130 @@ |
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/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* Version 2 as published by the Free Software Foundation. |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include <asm/fsl_ddr_dimm_params.h> |
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static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) |
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{ |
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i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); |
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} |
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unsigned int fsl_ddr_get_mem_data_rate(void) |
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{ |
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return get_ddr_freq(0); |
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} |
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void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, |
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unsigned int ctrl_num) |
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{ |
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unsigned int i; |
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unsigned int i2c_address = 0; |
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { |
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if (ctrl_num == 0 && i == 0) |
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i2c_address = SPD_EEPROM_ADDRESS1; |
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get_spd(&(ctrl_dimms_spd[i]), i2c_address); |
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} |
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} |
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typedef struct { |
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u32 datarate_mhz_low; |
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u32 datarate_mhz_high; |
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u32 n_ranks; |
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u32 clk_adjust; |
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u32 cpo; |
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u32 write_data_delay; |
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u32 force_2T; |
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} board_specific_parameters_t; |
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/* ranges for parameters:
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* wr_data_delay = 0-6 |
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* clk adjust = 0-8 |
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* cpo 2-0x1E (30) |
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*/ |
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/* XXX: these values need to be checked for all interleaving modes. */ |
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/* XXX: No reliable dual-rank 800 MHz setting has been found. It may
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* seem reliable, but errors will appear when memory intensive |
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* program is run. */ |
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/* XXX: Single rank at 800 MHz is OK. */ |
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const board_specific_parameters_t board_specific_parameters[][20] = { |
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{ |
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/* memory controller 0 */ |
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/* lo| hi| num| clk| cpo|wrdata|2T */ |
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/* mhz| mhz|ranks|adjst| | delay| */ |
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{ 0, 333, 2, 6, 7, 3, 0}, |
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{334, 400, 2, 6, 9, 3, 0}, |
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{401, 549, 2, 6, 11, 3, 0}, |
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{550, 680, 2, 1, 10, 5, 0}, |
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{681, 850, 2, 1, 12, 5, 1}, |
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{ 0, 333, 1, 6, 7, 3, 0}, |
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{334, 400, 1, 6, 9, 3, 0}, |
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{401, 549, 1, 6, 11, 3, 0}, |
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{550, 680, 1, 1, 10, 5, 0}, |
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{681, 850, 1, 1, 12, 5, 0} |
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}, |
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}; |
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void fsl_ddr_board_options(memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num) |
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{ |
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const board_specific_parameters_t *pbsp = |
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&(board_specific_parameters[ctrl_num][0]); |
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u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / |
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sizeof(board_specific_parameters[0][0]); |
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u32 i; |
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ulong ddr_freq; |
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/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
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* that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If |
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* there are two dimms in the controller, set odt_rd_cfg to 3 and |
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* odt_wr_cfg to 3 for the even CS, 0 for the odd CS. |
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*/ |
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
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if (i&1) { /* odd CS */ |
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popts->cs_local_opts[i].odt_rd_cfg = 0; |
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popts->cs_local_opts[i].odt_wr_cfg = 0; |
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} else { /* even CS */ |
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if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { |
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popts->cs_local_opts[i].odt_rd_cfg = 0; |
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popts->cs_local_opts[i].odt_wr_cfg = 4; |
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} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { |
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popts->cs_local_opts[i].odt_rd_cfg = 3; |
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popts->cs_local_opts[i].odt_wr_cfg = 3; |
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} |
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} |
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} |
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table. |
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*/ |
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ddr_freq = get_ddr_freq(0) / 1000000; |
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for (i = 0; i < num_params; i++) { |
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if (ddr_freq >= pbsp->datarate_mhz_low && |
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ddr_freq <= pbsp->datarate_mhz_high && |
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pdimm->n_ranks == pbsp->n_ranks) { |
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popts->clk_adjust = pbsp->clk_adjust; |
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popts->cpo_override = pbsp->cpo; |
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popts->write_data_delay = pbsp->write_data_delay; |
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popts->twoT_en = pbsp->force_2T; |
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} |
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pbsp++; |
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} |
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/*
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* Factors to consider for half-strength driver enable: |
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* - number of DIMMs installed |
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*/ |
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popts->half_strength_driver_enable = 0; |
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} |
@ -0,0 +1,42 @@ |
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/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/fsl_law.h> |
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#include <asm/mmu.h> |
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struct law_entry law_table[] = { |
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), |
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), |
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SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), |
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SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), |
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SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), |
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SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), |
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SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), |
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), |
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}; |
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int num_law_entries = ARRAY_SIZE(law_table); |
@ -0,0 +1,634 @@ |
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/*
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* Copyright 2007-2009 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <pci.h> |
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#include <asm/processor.h> |
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#include <asm/mmu.h> |
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#include <asm/cache.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/fsl_pci.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include <asm/io.h> |
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#include <miiphy.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#include <tsec.h> |
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#include <asm/fsl_law.h> |
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#include <asm/mp.h> |
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#include "../common/pixis.h" |
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#include "../common/sgmii_riser.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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phys_size_t fixed_sdram(void); |
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int checkboard(void) |
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{ |
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puts("Board: P2020DS "); |
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#ifdef CONFIG_PHYS_64BIT |
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puts("(36-bit addrmap) "); |
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#endif |
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printf("Sys ID: 0x%02x, " |
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"Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n", |
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in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), |
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in8(PIXIS_BASE + PIXIS_PVER)); |
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return 0; |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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phys_size_t dram_size = 0; |
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puts("Initializing...."); |
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#ifdef CONFIG_SPD_EEPROM |
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dram_size = fsl_ddr_sdram(); |
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#else |
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dram_size = fixed_sdram(); |
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, |
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dram_size, |
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LAW_TRGT_IF_DDR) < 0) { |
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printf("ERROR setting Local Access Windows for DDR\n"); |
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return 0; |
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}; |
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#endif |
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dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
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dram_size *= 0x100000; |
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puts(" DDR: "); |
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return dram_size; |
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} |
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#if !defined(CONFIG_SPD_EEPROM) |
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/*
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* Fixed sdram init -- doesn't use serial presence detect. |
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*/ |
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phys_size_t fixed_sdram(void) |
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{ |
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volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; |
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uint d_init; |
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
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ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; |
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ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; |
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ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL; |
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
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ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; |
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; |
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; |
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ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL; |
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ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL; |
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ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1; |
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ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4; |
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ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5; |
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if (!strcmp("performance", getenv("perf_mode"))) { |
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/* Performance Mode Values */ |
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ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF; |
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF; |
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ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF; |
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF; |
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF; |
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asm("sync;isync"); |
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udelay(500); |
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF; |
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} else { |
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/* Stable Mode Values */ |
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ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; |
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
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ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; |
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
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/* ECC will be assumed in stable mode */ |
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ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; |
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ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; |
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ddr->err_sbe = CONFIG_SYS_DDR_SBE; |
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asm("sync;isync"); |
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udelay(500); |
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
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} |
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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d_init = 1; |
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debug("DDR - 1st controller: memory initializing\n"); |
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/*
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* Poll until memory is initialized. |
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* 512 Meg at 400 might hit this 200 times or so. |
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*/ |
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) |
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udelay(1000); |
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debug("DDR: memory initialized\n\n"); |
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asm("sync; isync"); |
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udelay(500); |
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#endif |
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
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} |
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#endif |
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#ifdef CONFIG_PCIE1 |
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static struct pci_controller pcie1_hose; |
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#endif |
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|
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#ifdef CONFIG_PCIE2 |
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static struct pci_controller pcie2_hose; |
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#endif |
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|
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#ifdef CONFIG_PCIE3 |
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static struct pci_controller pcie3_hose; |
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#endif |
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int first_free_busno = 0; |
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#ifdef CONFIG_PCI |
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void pci_init_board(void) |
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{ |
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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uint devdisr = gur->devdisr; |
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; |
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; |
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|
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volatile ccsr_fsl_pci_t *pci; |
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struct pci_controller *hose; |
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int pcie_ep, pcie_configured; |
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struct pci_region *r; |
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/* u32 temp32; */ |
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|
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debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", |
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devdisr, io_sel, host_agent); |
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|
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) |
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printf(" eTSEC2 is in sgmii mode.\n"); |
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) |
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printf(" eTSEC3 is in sgmii mode.\n"); |
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|
||||
#ifdef CONFIG_PCIE2 |
||||
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; |
||||
hose = &pcie2_hose; |
||||
pcie_ep = (host_agent == 2) || (host_agent == 4) || |
||||
(host_agent == 6) || (host_agent == 0); |
||||
pcie_configured = (io_sel == 0x2) || (io_sel == 0xe); |
||||
r = hose->regions; |
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { |
||||
printf("\n PCIE2 connected to ULI as %s (base addr %x)", |
||||
pcie_ep ? "End Point" : "Root Complex", |
||||
(uint)pci); |
||||
if (pci->pme_msg_det) { |
||||
pci->pme_msg_det = 0xffffffff; |
||||
debug(" with errors. Clearing. Now 0x%08x", |
||||
pci->pme_msg_det); |
||||
} |
||||
printf("\n"); |
||||
|
||||
/* inbound */ |
||||
r += fsl_pci_setup_inbound_windows(r); |
||||
|
||||
/* outbound memory */ |
||||
pci_set_region(r++, |
||||
CONFIG_SYS_PCIE2_MEM_BUS, |
||||
CONFIG_SYS_PCIE2_MEM_PHYS, |
||||
CONFIG_SYS_PCIE2_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* outbound io */ |
||||
pci_set_region(r++, |
||||
CONFIG_SYS_PCIE2_IO_BUS, |
||||
CONFIG_SYS_PCIE2_IO_PHYS, |
||||
CONFIG_SYS_PCIE2_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = r - hose->regions; |
||||
hose->first_busno = first_free_busno; |
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr, |
||||
(int)&pci->cfg_data); |
||||
|
||||
fsl_pci_init(hose); |
||||
first_free_busno = hose->last_busno+1; |
||||
printf(" PCIE2 on bus %02x - %02x\n", |
||||
hose->first_busno, hose->last_busno); |
||||
|
||||
/*
|
||||
* The workaround doesn't work on p2020 because the location |
||||
* we try and read isn't valid on p2020, fix this later |
||||
*/ |
||||
#if 0 |
||||
/*
|
||||
* Activate ULI1575 legacy chip by performing a fake |
||||
* memory access. Needed to make ULI RTC work. |
||||
* Device 1d has the first on-board memory BAR. |
||||
*/ |
||||
|
||||
pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0), |
||||
PCI_BASE_ADDRESS_1, &temp32); |
||||
if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { |
||||
void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), |
||||
temp32, 4, 0); |
||||
debug(" uli1575 read to %p\n", p); |
||||
in_be32(p); |
||||
} |
||||
#endif |
||||
} else { |
||||
printf(" PCIE2: disabled\n"); |
||||
} |
||||
#else |
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCIE3 |
||||
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; |
||||
hose = &pcie3_hose; |
||||
pcie_ep = (host_agent == 0) || (host_agent == 3) || |
||||
(host_agent == 5) || (host_agent == 6); |
||||
pcie_configured = (io_sel == 0x2) || (io_sel == 0x4); |
||||
r = hose->regions; |
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { |
||||
printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)", |
||||
pcie_ep ? "End Point" : "Root Complex", |
||||
(uint)pci); |
||||
if (pci->pme_msg_det) { |
||||
pci->pme_msg_det = 0xffffffff; |
||||
debug(" with errors. Clearing. Now 0x%08x", |
||||
pci->pme_msg_det); |
||||
} |
||||
printf("\n"); |
||||
|
||||
/* inbound */ |
||||
r += fsl_pci_setup_inbound_windows(r); |
||||
|
||||
/* outbound memory */ |
||||
pci_set_region(r++, |
||||
CONFIG_SYS_PCIE3_MEM_BUS, |
||||
CONFIG_SYS_PCIE3_MEM_PHYS, |
||||
CONFIG_SYS_PCIE3_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* outbound io */ |
||||
pci_set_region(r++, |
||||
CONFIG_SYS_PCIE3_IO_BUS, |
||||
CONFIG_SYS_PCIE3_IO_PHYS, |
||||
CONFIG_SYS_PCIE3_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = r - hose->regions; |
||||
hose->first_busno = first_free_busno; |
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr, |
||||
(int)&pci->cfg_data); |
||||
|
||||
fsl_pci_init(hose); |
||||
|
||||
first_free_busno = hose->last_busno+1; |
||||
printf(" PCIE3 on bus %02x - %02x\n", |
||||
hose->first_busno, hose->last_busno); |
||||
|
||||
} else { |
||||
printf(" PCIE3: disabled\n"); |
||||
} |
||||
#else |
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; |
||||
hose = &pcie1_hose; |
||||
pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5); |
||||
pcie_configured = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF); |
||||
r = hose->regions; |
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { |
||||
printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)", |
||||
pcie_ep ? "End Point" : "Root Complex", |
||||
(uint)pci); |
||||
if (pci->pme_msg_det) { |
||||
pci->pme_msg_det = 0xffffffff; |
||||
debug(" with errors. Clearing. Now 0x%08x", |
||||
pci->pme_msg_det); |
||||
} |
||||
printf("\n"); |
||||
|
||||
/* inbound */ |
||||
r += fsl_pci_setup_inbound_windows(r); |
||||
|
||||
/* outbound memory */ |
||||
pci_set_region(r++, |
||||
CONFIG_SYS_PCIE1_MEM_BUS, |
||||
CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
CONFIG_SYS_PCIE1_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* outbound io */ |
||||
pci_set_region(r++, |
||||
CONFIG_SYS_PCIE1_IO_BUS, |
||||
CONFIG_SYS_PCIE1_IO_PHYS, |
||||
CONFIG_SYS_PCIE1_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = r - hose->regions; |
||||
hose->first_busno = first_free_busno; |
||||
|
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr, |
||||
(int)&pci->cfg_data); |
||||
|
||||
fsl_pci_init(hose); |
||||
|
||||
first_free_busno = hose->last_busno+1; |
||||
printf(" PCIE1 on bus %02x - %02x\n", |
||||
hose->first_busno, hose->last_busno); |
||||
|
||||
} else { |
||||
printf(" PCIE1: disabled\n"); |
||||
} |
||||
#else |
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ |
||||
#endif |
||||
} |
||||
#endif |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
||||
const u8 flash_esel = 2; |
||||
|
||||
/*
|
||||
* Remap Boot flash + PROMJET region to caching-inhibited |
||||
* so that flash can be erased properly. |
||||
*/ |
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */ |
||||
flush_dcache(); |
||||
invalidate_icache(); |
||||
|
||||
/* invalidate existing TLB entry for flash + promjet */ |
||||
disable_tlb(flash_esel); |
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_GET_CLK_FROM_ICS307 |
||||
/* decode S[0-2] to Output Divider (OD) */ |
||||
static unsigned char ics307_S_to_OD[] = { |
||||
10, 2, 8, 4, 5, 7, 3, 6 |
||||
}; |
||||
|
||||
/* Calculate frequency being generated by ICS307-02 clock chip based upon
|
||||
* the control bytes being programmed into it. */ |
||||
/* XXX: This function should probably go into a common library */ |
||||
static unsigned long |
||||
ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2) |
||||
{ |
||||
const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; |
||||
unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); |
||||
unsigned long RDW = cw2 & 0x7F; |
||||
unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; |
||||
unsigned long freq; |
||||
|
||||
/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ |
||||
|
||||
/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
|
||||
* cw1: V8 V7 V6 V5 V4 V3 V2 V1 |
||||
* cw2: V0 R6 R5 R4 R3 R2 R1 R0 |
||||
* |
||||
* R6:R0 = Reference Divider Word (RDW) |
||||
* V8:V0 = VCO Divider Word (VDW) |
||||
* S2:S0 = Output Divider Select (OD) |
||||
* F1:F0 = Function of CLK2 Output |
||||
* TTL = duty cycle |
||||
* C1:C0 = internal load capacitance for cyrstal |
||||
*/ |
||||
|
||||
/* Adding 1 to get a "nicely" rounded number, but this needs
|
||||
* more tweaking to get a "properly" rounded number. */ |
||||
|
||||
freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); |
||||
|
||||
debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, |
||||
freq); |
||||
return freq; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(ulong dummy) |
||||
{ |
||||
return gd->bus_clk; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(ulong dummy) |
||||
{ |
||||
return gd->mem_clk; |
||||
} |
||||
|
||||
unsigned long |
||||
calculate_board_sys_clk(ulong dummy) |
||||
{ |
||||
ulong val; |
||||
val = ics307_clk_freq( |
||||
in8(PIXIS_BASE + PIXIS_VSYSCLK0), |
||||
in8(PIXIS_BASE + PIXIS_VSYSCLK1), |
||||
in8(PIXIS_BASE + PIXIS_VSYSCLK2)); |
||||
debug("sysclk val = %lu\n", val); |
||||
return val; |
||||
} |
||||
|
||||
unsigned long |
||||
calculate_board_ddr_clk(ulong dummy) |
||||
{ |
||||
ulong val; |
||||
val = ics307_clk_freq( |
||||
in8(PIXIS_BASE + PIXIS_VDDRCLK0), |
||||
in8(PIXIS_BASE + PIXIS_VDDRCLK1), |
||||
in8(PIXIS_BASE + PIXIS_VDDRCLK2)); |
||||
debug("ddrclk val = %lu\n", val); |
||||
return val; |
||||
} |
||||
#else |
||||
unsigned long get_board_sys_clk(ulong dummy) |
||||
{ |
||||
u8 i; |
||||
ulong val = 0; |
||||
|
||||
i = in8(PIXIS_BASE + PIXIS_SPD); |
||||
i &= 0x07; |
||||
|
||||
switch (i) { |
||||
case 0: |
||||
val = 33333333; |
||||
break; |
||||
case 1: |
||||
val = 40000000; |
||||
break; |
||||
case 2: |
||||
val = 50000000; |
||||
break; |
||||
case 3: |
||||
val = 66666666; |
||||
break; |
||||
case 4: |
||||
val = 83333333; |
||||
break; |
||||
case 5: |
||||
val = 100000000; |
||||
break; |
||||
case 6: |
||||
val = 133333333; |
||||
break; |
||||
case 7: |
||||
val = 166666666; |
||||
break; |
||||
} |
||||
|
||||
return val; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(ulong dummy) |
||||
{ |
||||
u8 i; |
||||
ulong val = 0; |
||||
|
||||
i = in8(PIXIS_BASE + PIXIS_SPD); |
||||
i &= 0x38; |
||||
i >>= 3; |
||||
|
||||
switch (i) { |
||||
case 0: |
||||
val = 33333333; |
||||
break; |
||||
case 1: |
||||
val = 40000000; |
||||
break; |
||||
case 2: |
||||
val = 50000000; |
||||
break; |
||||
case 3: |
||||
val = 66666666; |
||||
break; |
||||
case 4: |
||||
val = 83333333; |
||||
break; |
||||
case 5: |
||||
val = 100000000; |
||||
break; |
||||
case 6: |
||||
val = 133333333; |
||||
break; |
||||
case 7: |
||||
val = 166666666; |
||||
break; |
||||
} |
||||
return val; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_TSEC_ENET |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
struct tsec_info_struct tsec_info[4]; |
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
int num = 0; |
||||
|
||||
#ifdef CONFIG_TSEC1 |
||||
SET_STD_TSEC_INFO(tsec_info[num], 1); |
||||
num++; |
||||
#endif |
||||
#ifdef CONFIG_TSEC2 |
||||
SET_STD_TSEC_INFO(tsec_info[num], 2); |
||||
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) |
||||
tsec_info[num].flags |= TSEC_SGMII; |
||||
num++; |
||||
#endif |
||||
#ifdef CONFIG_TSEC3 |
||||
SET_STD_TSEC_INFO(tsec_info[num], 3); |
||||
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) |
||||
tsec_info[num].flags |= TSEC_SGMII; |
||||
num++; |
||||
#endif |
||||
|
||||
if (!num) { |
||||
printf("No TSECs initialized\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_FSL_SGMII_RISER |
||||
fsl_sgmii_riser_init(tsec_info, num); |
||||
#endif |
||||
|
||||
tsec_eth_init(bis, tsec_info, num); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) |
||||
void ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
phys_addr_t base; |
||||
phys_size_t size; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
base = getenv_bootm_low(); |
||||
size = getenv_bootm_size(); |
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||
|
||||
#ifdef CONFIG_PCIE3 |
||||
ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); |
||||
#endif |
||||
#ifdef CONFIG_PCIE2 |
||||
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); |
||||
#endif |
||||
#ifdef CONFIG_PCIE1 |
||||
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); |
||||
#endif |
||||
#ifdef CONFIG_FSL_SGMII_RISER |
||||
fsl_sgmii_riser_fdt_fixup(blob); |
||||
#endif |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MP |
||||
void board_lmb_reserve(struct lmb *lmb) |
||||
{ |
||||
cpu_mp_lmb_reserve(lmb); |
||||
} |
||||
#endif |
@ -0,0 +1,95 @@ |
||||
/*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/* TLB 1 */ |
||||
/* *I*** - Covers boot page */ |
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, |
||||
0, 0, BOOKE_PAGESZ_4K, 1), |
||||
|
||||
/* *I*G* - CCSRBAR */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
/* W**G* - Flash/promjet, localbus */ |
||||
/* This will be changed to *I*G* after relocation to RAM. */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/* *I*G* - PCI */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
/* *I*G* - PCI */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, |
||||
CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, |
||||
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/* *I*G* - PCI I/O */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_256K, 1), |
||||
|
||||
/* *I*G - NAND */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 8, BOOKE_PAGESZ_4K, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
@ -0,0 +1,143 @@ |
||||
/* |
||||
* Copyright 2007-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
PHDRS |
||||
{ |
||||
text PT_LOAD; |
||||
bss PT_LOAD; |
||||
} |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} :text |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.eh_frame) |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} :text |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
.bootpg ADDR(.text) + 0x7f000 : |
||||
{ |
||||
cpu/mpc85xx/start.o (.bootpg) |
||||
} :text = 0xffff |
||||
|
||||
.resetvec ADDR(.text) + 0x7fffc : |
||||
{ |
||||
*(.resetvec) |
||||
} :text = 0xffff |
||||
|
||||
. = ADDR(.text) + 0x80000; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} :bss |
||||
|
||||
. = ALIGN(4); |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,741 @@ |
||||
/*
|
||||
* Copyright 2007-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* p2020ds board configuration file |
||||
* |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
||||
#define CONFIG_P2020 1 |
||||
#define CONFIG_P2020DS 1 |
||||
#define CONFIG_MP 1 /* support multiple processors */ |
||||
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ |
||||
|
||||
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
||||
#define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
||||
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
||||
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ |
||||
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ |
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
||||
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
||||
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* When initializing flash, if we cannot find the manufacturer ID, |
||||
* assume this is the AMD flash associated with the CDS board. |
||||
* This allows booting from a promjet. |
||||
*/ |
||||
#define CONFIG_ASSUME_AMD_FLASH |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned long calculate_board_sys_clk(unsigned long dummy); |
||||
extern unsigned long calculate_board_ddr_clk(unsigned long dummy); |
||||
/* extern unsigned long get_board_sys_clk(unsigned long dummy); */ |
||||
/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */ |
||||
#endif |
||||
#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */ |
||||
#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */ |
||||
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
||||
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq |
||||
from ICS307 instead of switches */ |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1 |
||||
|
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_ADDR_MAP 1 |
||||
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x7fffffff |
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */ |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ |
||||
#else |
||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
||||
#endif |
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
||||
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) |
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) |
||||
|
||||
/* DDR Setup */ |
||||
#define CONFIG_SYS_DDR_TLB_START 9 |
||||
#define CONFIG_VERY_BIG_RAM |
||||
#define CONFIG_FSL_DDR3 1 |
||||
#undef CONFIG_FSL_DDR_INTERACTIVE |
||||
|
||||
// #define CONFIG_DDR_ECC /* ECC will be enabled based on perf_mode environment variable */
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1 |
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
||||
|
||||
/* I2C addresses of SPD EEPROMs */ |
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ |
||||
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
||||
|
||||
/* These are used when DDR doesn't use SPD. */ |
||||
//#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
|
||||
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ |
||||
|
||||
/* Default settings for "stable" mode */ |
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
||||
#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 |
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
||||
#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 |
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00330804 |
||||
#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 |
||||
#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 |
||||
#define CONFIG_SYS_DDR_MODE_1 0x00421422 |
||||
#define CONFIG_SYS_DDR_MODE_2 0x00000000 |
||||
#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 |
||||
#define CONFIG_SYS_DDR_INTERVAL 0x61800100 |
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 |
||||
#define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
||||
#define CONFIG_SYS_DDR_TIMING_5 0x03402400 |
||||
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 |
||||
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 |
||||
#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ |
||||
#define CONFIG_SYS_DDR_CONTROL2 0x24400011 |
||||
#define CONFIG_SYS_DDR_CDR1 0x00040000 |
||||
#define CONFIG_SYS_DDR_CDR2 0x00000000 |
||||
|
||||
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
||||
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
||||
#define CONFIG_SYS_DDR_SBE 0x00010000 |
||||
|
||||
/* Settings that differ for "performance" mode */ |
||||
#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ |
||||
#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ |
||||
#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 |
||||
#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 |
||||
#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce |
||||
#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ |
||||
|
||||
/*
|
||||
* The following set of values were tested for DDR2 |
||||
* with a DDR3 to DDR2 interposer |
||||
* |
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
||||
#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 |
||||
#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 |
||||
#define CONFIG_SYS_DDR_MODE_1 0x00480432 |
||||
#define CONFIG_SYS_DDR_MODE_2 0x00000000 |
||||
#define CONFIG_SYS_DDR_INTERVAL 0x06180100 |
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 |
||||
#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
||||
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
||||
#define CONFIG_SYS_DDR_CONTROL 0xC3008000 |
||||
#define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
||||
* |
||||
*/ |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
/*
|
||||
* Memory map |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
||||
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
||||
* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable |
||||
* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable |
||||
* |
||||
* Localbus cacheable (TBD) |
||||
* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
||||
* |
||||
* Localbus non-cacheable |
||||
* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable |
||||
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
||||
* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
||||
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
||||
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
||||
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
||||
*/ |
||||
|
||||
/*
|
||||
* Local Bus Definitions |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
||||
#else |
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
||||
#endif |
||||
|
||||
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) |
||||
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
||||
#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
||||
#define CONFIG_SYS_FLASH_QUIET_TEST |
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||
#undef CONFIG_SYS_FLASH_CHECKSUM |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
||||
|
||||
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
||||
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define PIXIS_BASE_PHYS 0xfffdf0000ull |
||||
#else |
||||
#define PIXIS_BASE_PHYS PIXIS_BASE |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
||||
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
||||
|
||||
#define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
||||
#define PIXIS_VER 0x1 /* Board version at offset 1 */ |
||||
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ |
||||
#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ |
||||
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ |
||||
#define PIXIS_PWR 0x5 /* PIXIS Power status register */ |
||||
#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ |
||||
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
||||
#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ |
||||
#define PIXIS_VCTL 0x10 /* VELA Control Register */ |
||||
#define PIXIS_VSTAT 0x11 /* VELA Status Register */ |
||||
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
||||
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
||||
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ |
||||
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
||||
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
||||
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
||||
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ |
||||
#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */ |
||||
#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */ |
||||
#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */ |
||||
#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */ |
||||
#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */ |
||||
#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */ |
||||
|
||||
#define PIXIS_VWATCH 0x24 /* Watchdog Register */ |
||||
#define PIXIS_LED 0x25 /* LED Register */ |
||||
|
||||
/* old pixis referenced names */ |
||||
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
||||
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
||||
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
||||
#define PIXIS_VSPEED2_TSEC1SER 0x8 |
||||
#define PIXIS_VSPEED2_TSEC2SER 0x4 |
||||
#define PIXIS_VSPEED2_TSEC3SER 0x2 |
||||
#define PIXIS_VSPEED2_TSEC4SER 0x1 |
||||
#define PIXIS_VCFGEN1_TSEC1SER 0x20 |
||||
#define PIXIS_VCFGEN1_TSEC2SER 0x20 |
||||
#define PIXIS_VCFGEN1_TSEC3SER 0x20 |
||||
#define PIXIS_VCFGEN1_TSEC4SER 0x20 |
||||
#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ |
||||
| PIXIS_VSPEED2_TSEC2SER \
|
||||
| PIXIS_VSPEED2_TSEC3SER \
|
||||
| PIXIS_VSPEED2_TSEC4SER) |
||||
#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ |
||||
| PIXIS_VCFGEN1_TSEC2SER \
|
||||
| PIXIS_VCFGEN1_TSEC3SER \
|
||||
| PIXIS_VCFGEN1_TSEC4SER) |
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
||||
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0xffa00000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull |
||||
#else |
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
||||
#endif |
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
||||
CONFIG_SYS_NAND_BASE + 0x40000, \
|
||||
CONFIG_SYS_NAND_BASE + 0x80000,\
|
||||
CONFIG_SYS_NAND_BASE + 0xC0000} |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 4 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_CMD_NAND 1 |
||||
#define CONFIG_NAND_FSL_ELBC 1 |
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
||||
|
||||
/* NAND flash config */ |
||||
#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
||||
| OR_FCM_PGS /* Large Page*/ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR) |
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ |
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ |
||||
|
||||
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ |
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ |
||||
#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ |
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ |
||||
|
||||
#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ |
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ |
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2 |
||||
* shorted - index 1 |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#ifdef CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/*
|
||||
* Pass open firmware flat tree |
||||
*/ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF 1 |
||||
#define CONFIG_SYS_64BIT_STRTOUL 1 |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT 1 |
||||
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ |
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000 |
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100 |
||||
|
||||
/*
|
||||
* I2C2 EEPROM |
||||
*/ |
||||
#define CONFIG_ID_EEPROM |
||||
#ifdef CONFIG_ID_EEPROM |
||||
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||
#endif |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Memory space is mapped 1-1, but I/O space must start from 0. |
||||
*/ |
||||
|
||||
/* controller 3, Slot 1, tgtid 3, Base address b000 */ |
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 2, direct to uli, tgtid 2, Base address 9000 */ |
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 1, Slot 2, tgtid 1, Base address a000 */ |
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
/*PCIE video card used*/ |
||||
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
||||
|
||||
/* video */ |
||||
#define CONFIG_VIDEO |
||||
|
||||
#if defined(CONFIG_VIDEO) |
||||
#define CONFIG_BIOSEMU |
||||
#define CONFIG_CFB_CONSOLE |
||||
#define CONFIG_VIDEO_SW_CURSOR |
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE |
||||
#define CONFIG_ATI_RADEON_FB |
||||
#define CONFIG_VIDEO_LOGO |
||||
/*#define CONFIG_CONSOLE_CURSOR*/ |
||||
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
||||
#endif |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
#define CONFIG_RTL8139 |
||||
|
||||
#ifdef CONFIG_RTL8139 |
||||
/* This macro is used by RTL8139 but not defined in PPC architecture */ |
||||
#define KSEG1ADDR(x) (x) |
||||
#define _IO_BASE 0x00000000 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
||||
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS |
||||
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
||||
#endif |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_SCSI_AHCI |
||||
|
||||
#ifdef CONFIG_SCSI_AHCI |
||||
#define CONFIG_SATA_ULI5288 |
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1 |
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) |
||||
#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE |
||||
#endif /* SCSI */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
||||
#define CONFIG_TSEC1 1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC1" |
||||
#define CONFIG_TSEC2 1 |
||||
#define CONFIG_TSEC2_NAME "eTSEC2" |
||||
#define CONFIG_TSEC3 1 |
||||
#define CONFIG_TSEC3_NAME "eTSEC3" |
||||
|
||||
#define CONFIG_PIXIS_SGMII_CMD |
||||
#define CONFIG_FSL_SGMII_RISER 1 |
||||
#define SGMII_RISER_PHY_OFFSET 0x1b |
||||
|
||||
#ifdef CONFIG_FSL_SGMII_RISER |
||||
#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ |
||||
#endif |
||||
|
||||
#define TSEC1_PHY_ADDR 0 |
||||
#define TSEC2_PHY_ADDR 1 |
||||
#define TSEC3_PHY_ADDR 2 |
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
|
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define TSEC3_PHYIDX 0 |
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1" |
||||
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
||||
#define CONFIG_ENV_ADDR 0xfff80000 |
||||
#else |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
||||
#endif |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_SETEXPR |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_BEDBUG |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_SCSI |
||||
#define CONFIG_CMD_EXT2 |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
/* The mac addresses for all ethernet interface */ |
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD |
||||
#define CONFIG_HAS_ETH2 |
||||
#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD |
||||
#define CONFIG_HAS_ETH3 |
||||
#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD |
||||
#endif |
||||
|
||||
#define CONFIG_IPADDR 192.168.1.254 |
||||
|
||||
#define CONFIG_HOSTNAME unknown |
||||
#define CONFIG_ROOTPATH /opt/nfsroot |
||||
#define CONFIG_BOOTFILE uImage |
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
||||
|
||||
#define CONFIG_SERVERIP 192.168.1.1 |
||||
#define CONFIG_GATEWAYIP 192.168.1.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
|
||||
/* default location for tftp and bootm */ |
||||
#define CONFIG_LOADADDR 1000000 |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"perf_mode=stable\0" \
|
||||
"memctl_intlv_ctl=2\0" \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=p2020ds/ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=p2020ds/p2020ds.dtb\0" \
|
||||
"bdev=sda3\0" |
||||
|
||||
#define CONFIG_HDBOOT \ |
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue