As said in the SAMA5D2 datasheet, the PLLA clock must be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>master
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/*
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* Copyright (C) 2018 Microhip / Atmel Corporation |
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* Wenyou.Yang <wenyou.yang@microchip.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <clk-uclass.h> |
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#include <dm/device.h> |
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#include <linux/io.h> |
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#include <mach/at91_pmc.h> |
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#include "pmc.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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static int at91_plladiv_clk_enable(struct clk *clk) |
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{ |
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return 0; |
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} |
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static ulong at91_plladiv_clk_get_rate(struct clk *clk) |
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{ |
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struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
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struct at91_pmc *pmc = plat->reg_base; |
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struct clk source; |
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ulong clk_rate; |
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int ret; |
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ret = clk_get_by_index(clk->dev, 0, &source); |
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if (ret) |
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return -EINVAL; |
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clk_rate = clk_get_rate(&source); |
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if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2) |
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clk_rate /= 2; |
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return clk_rate; |
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} |
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static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate) |
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{ |
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struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
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struct at91_pmc *pmc = plat->reg_base; |
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struct clk source; |
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ulong parent_rate; |
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int ret; |
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ret = clk_get_by_index(clk->dev, 0, &source); |
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if (ret) |
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return -EINVAL; |
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parent_rate = clk_get_rate(&source); |
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if ((parent_rate != rate) && ((parent_rate) / 2 != rate)) |
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return -EINVAL; |
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if (parent_rate != rate) { |
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writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2), |
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&pmc->mckr); |
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} |
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return 0; |
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} |
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static struct clk_ops at91_plladiv_clk_ops = { |
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.enable = at91_plladiv_clk_enable, |
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.get_rate = at91_plladiv_clk_get_rate, |
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.set_rate = at91_plladiv_clk_set_rate, |
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}; |
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static int at91_plladiv_clk_probe(struct udevice *dev) |
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{ |
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return at91_pmc_core_probe(dev); |
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} |
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static const struct udevice_id at91_plladiv_clk_match[] = { |
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{ .compatible = "atmel,at91sam9x5-clk-plldiv" }, |
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{} |
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}; |
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U_BOOT_DRIVER(at91_plladiv_clk) = { |
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.name = "at91-plladiv-clk", |
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.id = UCLASS_CLK, |
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.of_match = at91_plladiv_clk_match, |
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.probe = at91_plladiv_clk_probe, |
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.platdata_auto_alloc_size = sizeof(struct pmc_platdata), |
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.ops = &at91_plladiv_clk_ops, |
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}; |
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