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rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE

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RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit
0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and
introduces random delays and data lose.

This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE
with the right shift.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
master
Romain Perier 8 years ago committed by Simon Glass
parent cf35242a3e
commit fefe9d06bd
1 changed files with 1 additions and 1 deletions
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  1. 2
      arch/arm/include/asm/arch-rockchip/grf_rk3288.h

2
arch/arm/include/asm/arch-rockchip/grf_rk3288.h
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@ -813,7 +813,7 @@ enum {
(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
RK3288_CLK_RX_DL_CFG_GMAC_MASK =

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