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powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target

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Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:

		setenv bootmaster SRIO1
		saveenv

The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
	1. Reduce a build configuration item in boards.cfg file.
	   No longer need to build a special image for master, just use a
	   normal target image and set the "bootmaster" variable.
	2. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just set the corresponding value to "bootmaster"
	   based on the using SRIO port.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
master
Liu Gang 13 years ago committed by Andy Fleming
parent 51928df64c
commit ff65f12699
6 changed files with 129 additions and 128 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 17
      arch/powerpc/cpu/mpc85xx/cpu_init.c
  2. 137
      arch/powerpc/cpu/mpc8xxx/srio.c
  3. 8
      arch/powerpc/include/asm/fsl_srio.h
  4. 4
      boards.cfg
  5. 59
      include/configs/P2041RDB.h
  6. 32
      include/configs/corenet_ds.h

17
arch/powerpc/cpu/mpc85xx/cpu_init.c
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@ -480,11 +480,18 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
#ifdef CONFIG_SRIOBOOT_MASTER
srio_boot_master();
#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
srio_boot_master_release_slave();
#endif
#ifdef CONFIG_FSL_CORENET
char *s = getenv("bootmaster");
if (s) {
if (!strcmp(s, "SRIO1")) {
srio_boot_master(1);
srio_boot_master_release_slave(1);
}
if (!strcmp(s, "SRIO2")) {
srio_boot_master(2);
srio_boot_master_release_slave(2);
}
}
#endif
#endif

137
arch/powerpc/cpu/mpc8xxx/srio.c
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@ -95,126 +95,92 @@ void srio_init(void)
}
}
#ifdef CONFIG_SRIOBOOT_MASTER
void srio_boot_master(void)
#ifdef CONFIG_FSL_CORENET
void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
out_be32((void *)&srio->impl.port[port - 1].ptaacr,
SRIO_PORT_ACCEPT_ALL);
debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
CONFIG_SRIOBOOT_MASTER_PORT);
debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
/* configure inbound window for slave's ucode */
debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; "
/* configure inbound window for slave's ucode and ENV */
debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar,
CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar,
CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
/* configure inbound window for slave's ENV */
debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; "
"Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n",
CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar,
CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar,
CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar,
(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_PHYS,
(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_BUS,
CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_BUS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_SIZE));
}
#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
void srio_boot_master_release_slave(void)
void srio_boot_master_release_slave(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
u32 escsr;
debug("SRIOBOOT - MASTER: "
"Check the port status and release slave core ...\n");
escsr = in_be32((void *)&srio->lp_serial
.port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr);
escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
if (escsr & 0x2) {
if (escsr & 0x10100) {
debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
CONFIG_SRIOBOOT_MASTER_PORT);
port);
} else {
debug("SRIOBOOT - MASTER: "
"Port [ %d ] is ready, now release slave's core ...\n",
CONFIG_SRIOBOOT_MASTER_PORT);
"Port [ %d ] is ready, now release slave's core ...\n",
port);
/*
* configure outbound window
* with maintenance attribute to set slave's LCSBA1CSR
*/
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowtar, 0);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowtear, 0);
if (CONFIG_SRIOBOOT_MASTER_PORT)
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
if (port - 1)
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowbar,
CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
else
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowbar,
CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowar,
SRIO_OB_ATMU_AR_MAINT
| atmu_size_mask(SRIO_MAINT_WIN_SIZE));
@ -223,27 +189,22 @@ void srio_boot_master_release_slave(void)
* configure outbound window
* with R/W attribute to set slave's BRR
*/
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowtar,
SRIO_LCSBA1CSR >> 9);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowtear, 0);
if (CONFIG_SRIOBOOT_MASTER_PORT)
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
if (port - 1)
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowbar,
(CONFIG_SYS_SRIO2_MEM_PHYS
+ SRIO_MAINT_WIN_SIZE) >> 12);
else
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowbar,
(CONFIG_SYS_SRIO1_MEM_PHYS
+ SRIO_MAINT_WIN_SIZE) >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowar,
SRIO_OB_ATMU_AR_RW
| atmu_size_mask(SRIO_RW_WIN_SIZE));
@ -252,7 +213,7 @@ void srio_boot_master_release_slave(void)
* Set the LCSBA1CSR register in slave
* by the maint-outbound window
*/
if (CONFIG_SRIOBOOT_MASTER_PORT) {
if (port - 1) {
out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET,
SRIO_LCSBA1CSR);
@ -289,8 +250,6 @@ void srio_boot_master_release_slave(void)
"Release slave successfully! Now the slave should start up!\n");
}
} else
debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n",
CONFIG_SRIOBOOT_MASTER_PORT);
debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);
}
#endif
#endif

8
arch/powerpc/include/asm/fsl_srio.h
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@ -55,10 +55,8 @@ enum atmu_size {
#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1))
extern void srio_init(void);
#ifdef CONFIG_SRIOBOOT_MASTER
extern void srio_boot_master(void);
#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
extern void srio_boot_master_release_slave(void);
#endif
#ifdef CONFIG_FSL_CORENET
extern void srio_boot_master(int port);
extern void srio_boot_master_release_slave(int port);
#endif
#endif

4
boards.cfg
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@ -787,12 +787,12 @@ P2041RDB_NAND powerpc mpc85xx p2041rdb freescale
P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT
P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P2041RDB_SRIOBOOT_SLAVE powerpc mpc85xx p2041rdb freescale - P2041RDB:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P3041DS powerpc mpc85xx corenet_ds freescale
P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT
P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER
P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P3060QDS powerpc mpc85xx p3060qds freescale
P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
@ -801,14 +801,12 @@ P4080DS powerpc mpc85xx corenet_ds freesca
P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT
P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER
P4080DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P5020DS powerpc mpc85xx corenet_ds freescale
P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER
P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
stxgp3 powerpc mpc85xx stxgp3 stx

59
include/configs/P2041RDB.h
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@ -36,6 +36,15 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifdef CONFIG_SRIOBOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_NO_FLASH
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
@ -73,7 +82,7 @@
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
#ifndef CONFIG_RAMBOOT_PBL
#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIOBOOT_SLAVE)
#define CONFIG_ENV_IS_NOWHERE
#endif
#else
@ -104,8 +113,12 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIOBOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
@ -374,6 +387,38 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 0xfef080000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 0xfff80000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2 0x3fff80000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_PHYS 0xfef040000ull
#define CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4
#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */
/*
* SRIOBOOT - SLAVE
*/
#ifdef CONFIG_SRIOBOOT_SLAVE
/* slave port for srioboot */
#define CONFIG_SRIOBOOT_SLAVE_PORT0
/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
#endif
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
@ -485,6 +530,16 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIOBOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* in two corenet boards, slave's ucode could be stored in master's memory
* space, the address can be mapped from slave TLB->slave LAW->
* slave SRIO outbound window->master inbound window->master LAW->
* the ucode address in master's NOR flash.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000

32
include/configs/corenet_ds.h
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@ -389,40 +389,24 @@
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* SRIOBOOT - MASTER
*/
#ifdef CONFIG_SRIOBOOT_MASTER
/* master port for srioboot*/
#define CONFIG_SRIOBOOT_MASTER_PORT 0
/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 0xfef080000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 0xfff80000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2 0x3fff80000ull
/*
* for slave UCODE instored in master memory space,
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull
#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull
#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */
/*
* for slave ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull
#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull
#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */
#define CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_PHYS 0xfef040000ull
#define CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF
#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4
#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */
#endif
/*
* SRIOBOOT - SLAVE

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