arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory

With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.

This will be the new structure:

     drivers/ddr/marvell/axp
     Supporting Armada XP (AXP) devices (and perhaps Armada 370)

     drivers/ddr/marvell/a38x
     Supporting Armada 38x devices (and perhaps Armada 39x)

Signed-off-by: Stefan Roese <sr@denx.de>
master
Stefan Roese 9 years ago committed by Luka Perkov
parent edb4702533
commit ff9112df8b
  1. 2
      arch/arm/mach-mvebu/include/mach/cpu.h
  2. 2
      arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
  3. 0
      drivers/ddr/marvell/axp/Makefile
  4. 0
      drivers/ddr/marvell/axp/ddr3_axp.h
  5. 0
      drivers/ddr/marvell/axp/ddr3_axp_config.h
  6. 0
      drivers/ddr/marvell/axp/ddr3_axp_mc_static.h
  7. 0
      drivers/ddr/marvell/axp/ddr3_axp_training_static.h
  8. 0
      drivers/ddr/marvell/axp/ddr3_axp_vars.h
  9. 0
      drivers/ddr/marvell/axp/ddr3_dfs.c
  10. 0
      drivers/ddr/marvell/axp/ddr3_dqs.c
  11. 0
      drivers/ddr/marvell/axp/ddr3_hw_training.c
  12. 0
      drivers/ddr/marvell/axp/ddr3_hw_training.h
  13. 0
      drivers/ddr/marvell/axp/ddr3_init.c
  14. 0
      drivers/ddr/marvell/axp/ddr3_init.h
  15. 0
      drivers/ddr/marvell/axp/ddr3_patterns_64bit.h
  16. 0
      drivers/ddr/marvell/axp/ddr3_pbs.c
  17. 0
      drivers/ddr/marvell/axp/ddr3_read_leveling.c
  18. 0
      drivers/ddr/marvell/axp/ddr3_sdram.c
  19. 0
      drivers/ddr/marvell/axp/ddr3_spd.c
  20. 0
      drivers/ddr/marvell/axp/ddr3_write_leveling.c
  21. 0
      drivers/ddr/marvell/axp/xor.c
  22. 0
      drivers/ddr/marvell/axp/xor.h
  23. 0
      drivers/ddr/marvell/axp/xor_regs.h
  24. 2
      include/configs/db-mv784mp-gp.h
  25. 2
      include/configs/maxbcm.h
  26. 2
      scripts/Makefile.spl

@ -125,7 +125,7 @@ int serdes_phy_config(void);
/*
* DDR3 init / training code ported from Marvell bin_hdr. Now
* available in mainline U-Boot in:
* drivers/ddr/mvebu/
* drivers/ddr/marvell
*/
int ddr3_init(void);
#endif /* __ASSEMBLY__ */

@ -7,7 +7,7 @@
#ifndef __HIGHSPEED_ENV_SPEC_H
#define __HIGHSPEED_ENV_SPEC_H
#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
#include "../../../drivers/ddr/marvell/axp/ddr3_hw_training.h"
typedef enum {
SERDES_UNIT_UNCONNECTED = 0x0,

@ -138,7 +138,7 @@
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR
#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_SPD_EEPROM 0x4e
#endif /* _CONFIG_DB_MV7846MP_GP_H */

@ -108,7 +108,7 @@
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR
#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
#endif /* _CONFIG_DB_MV7846MP_GP_H */

@ -59,7 +59,7 @@ libs-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/
libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/
libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/
libs-$(CONFIG_SYS_MVEBU_DDR) += drivers/ddr/mvebu/
libs-$(CONFIG_SYS_MVEBU_DDR_AXP) += drivers/ddr/marvell/axp/
libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/
libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/
libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/

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