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@ -71,7 +71,7 @@ u32 get_mcu_main_clk(void) |
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reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >> |
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MXC_CCM_CACRR_ARM_PODF_OFFSET; |
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); |
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); |
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return freq / (reg + 1); |
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} |
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@ -84,14 +84,14 @@ static u32 get_periph_clk(void) |
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reg = __raw_readl(&mxc_ccm->cbcdr); |
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if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL)) |
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return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); |
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return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK); |
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reg = __raw_readl(&mxc_ccm->cbcmr); |
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switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> |
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MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { |
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case 0: |
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return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); |
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return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); |
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case 1: |
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return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ); |
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return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK); |
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default: |
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return 0; |
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} |
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@ -146,15 +146,15 @@ static u32 get_uart_clk(void) |
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MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) { |
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case 0x0: |
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freq = decode_pll(mxc_plls[PLL1_CLOCK], |
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CONFIG_MX51_HCLK_FREQ); |
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CONFIG_SYS_MX5_HCLK); |
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break; |
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case 0x1: |
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freq = decode_pll(mxc_plls[PLL2_CLOCK], |
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CONFIG_MX51_HCLK_FREQ); |
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CONFIG_SYS_MX5_HCLK); |
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break; |
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case 0x2: |
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freq = decode_pll(mxc_plls[PLL3_CLOCK], |
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CONFIG_MX51_HCLK_FREQ); |
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CONFIG_SYS_MX5_HCLK); |
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break; |
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default: |
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return 66500000; |
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@ -181,7 +181,7 @@ u32 get_lp_apm(void) |
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u32 ccsr = __raw_readl(&mxc_ccm->ccsr); |
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if (((ccsr >> 9) & 1) == 0) |
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ret_val = CONFIG_MX51_HCLK_FREQ; |
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ret_val = CONFIG_SYS_MX5_HCLK; |
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else |
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ret_val = ((32768 * 1024)); |
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@ -207,17 +207,17 @@ u32 imx_get_cspiclk(void) |
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switch (clk_sel) { |
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case 0: |
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ret_val = decode_pll(mxc_plls[PLL1_CLOCK], |
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CONFIG_MX51_HCLK_FREQ) / |
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CONFIG_SYS_MX5_HCLK) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case 1: |
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ret_val = decode_pll(mxc_plls[PLL2_CLOCK], |
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CONFIG_MX51_HCLK_FREQ) / |
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CONFIG_SYS_MX5_HCLK) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case 2: |
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ret_val = decode_pll(mxc_plls[PLL3_CLOCK], |
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CONFIG_MX51_HCLK_FREQ) / |
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CONFIG_SYS_MX5_HCLK) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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default: |
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@ -248,7 +248,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) |
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return imx_get_cspiclk(); |
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case MXC_FEC_CLK: |
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return decode_pll(mxc_plls[PLL1_CLOCK], |
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CONFIG_MX51_HCLK_FREQ); |
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CONFIG_SYS_MX5_HCLK); |
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default: |
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break; |
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} |
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@ -269,16 +269,16 @@ u32 imx_get_fecclk(void) |
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/*
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* Dump some core clockes. |
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*/ |
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int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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u32 freq; |
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); |
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printf("mx51 pll1: %dMHz\n", freq / 1000000); |
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freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); |
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printf("mx51 pll2: %dMHz\n", freq / 1000000); |
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freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ); |
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printf("mx51 pll3: %dMHz\n", freq / 1000000); |
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); |
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printf("pll1: %dMHz\n", freq / 1000000); |
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freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK); |
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printf("pll2: %dMHz\n", freq / 1000000); |
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freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK); |
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printf("pll3: %dMHz\n", freq / 1000000); |
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printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); |
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printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); |
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@ -288,7 +288,7 @@ int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] |
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/***************************************************/ |
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U_BOOT_CMD( |
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clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks, |
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"display mx51 clocks\n", |
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clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks, |
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"display clocks\n", |
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"" |
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); |