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Cleaned up some 85xx PCI bugs

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* Cleaned up the CDS PCI Config Tables and added NULL entries to
  the end
* Fixed PCIe LAWBAR assignemt to use the cpu-relative address
* Fixed 85xx PCI code to assign powar region sizes based on the
  config values (rather than hard-coding them)
* Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address

Signed-off-by: Andy Fleming <afleming@freescale.com>
master
Andy Fleming 18 years ago committed by Andrew Fleming-AFLEMING
parent 6743105988
commit ffa621a0d1
6 changed files with 28 additions and 19 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 9
      board/cds/mpc8541cds/mpc8541cds.c
  2. 2
      board/cds/mpc8548cds/init.S
  3. 9
      board/cds/mpc8548cds/mpc8548cds.c
  4. 11
      board/cds/mpc8555cds/mpc8555cds.c
  5. 8
      cpu/mpc85xx/pci.c
  6. 8
      include/configs/MPC8548CDS.h

9
board/cds/mpc8541cds/mpc8541cds.c
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@ -477,11 +477,14 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
mpc85xx_config_via_usbide, {0,0,0}},
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
mpc85xx_config_via_power, {0,0,0}},
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
{},
};
static struct pci_controller hose[] = {

2
board/cds/mpc8548cds/init.S
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@ -248,7 +248,7 @@ tlb1_entry:
#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR7 ((CFG_PEX_IO_BASE>>12) & 0xfffff)
#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)

9
board/cds/mpc8548cds/mpc8548cds.c
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@ -310,11 +310,14 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
mpc85xx_config_via_usbide, {0,0,0}},
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
mpc85xx_config_via_power, {0,0,0}},
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
{},
};
static struct pci_controller hose[] = {

11
board/cds/mpc8555cds/mpc8555cds.c
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@ -474,11 +474,14 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
mpc85xx_config_via_usbide, {0,0,0}},
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
mpc85xx_config_via_power, {0,0,0}},
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
{},
};
@ -487,7 +490,7 @@ static struct pci_controller hose[] = {
config_table: pci_mpc85xxcds_config_table,
},
#ifdef CONFIG_MPC85XX_PCI2
{ }
{},
#endif
};

8
cpu/mpc85xx/pci.c
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@ -90,14 +90,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
pcix->powbear1 = 0x00000000;
pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
POWAR_MEM_WRITE | POWAR_MEM_512M);
POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1));
pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
pcix->potear2 = 0x00000000;
pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
pcix->powbear2 = 0x00000000;
pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
POWAR_IO_WRITE | POWAR_IO_1M);
POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1));
pcix->pitar1 = 0x00000000;
pcix->piwbar1 = 0x00000000;
@ -175,14 +175,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
pcix2->powbear1 = 0x00000000;
pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
POWAR_MEM_WRITE | POWAR_MEM_512M);
POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1));
pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
pcix2->potear2 = 0x00000000;
pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
pcix2->powbear2 = 0x00000000;
pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
POWAR_IO_WRITE | POWAR_IO_1M);
POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1));
pcix2->pitar1 = 0x00000000;
pcix2->piwbar1 = 0x00000000;

8
include/configs/MPC8548CDS.h
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@ -352,16 +352,16 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI2_MEM_BASE 0x90000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI2_IO_BASE 0xe2800000
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xe2800000
#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */
#define CFG_PEX_MEM_BASE 0xa0000000
#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PEX_IO_BASE 0xe3000000
#define CFG_PEX_IO_PHYS CFG_PEX_IO_BASE
#define CFG_PEX_IO_SIZE 0x1000000 /* 16M */
#define CFG_PEX_IO_BASE 0x00000000
#define CFG_PEX_IO_PHYS 0xe3000000
#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */
/*
* RapidIO MMU

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