Commit Graph

5 Commits (02bd475e343582b3c915b94ef4016d5876d4a4f1)

Author SHA1 Message Date
Dave Liu b4983e16d1 fsl-ddr: use the 1T timing as default configuration 16 years ago
Wolfgang Denk 3cbd823116 Coding Style cleanup, update CHANGELOG 16 years ago
Haiying Wang c21617fd26 Add DDR options setting on MPC8641HPCN board 16 years ago
Haiying Wang dfb49108e4 Pass dimm parameters to populate populate controller options 16 years ago
Kumar Gala 6a8e569293 FSL DDR: Convert MPC8641HPCN to new DDR code. 17 years ago