3 Commits (079589bcfb24ba11068460276a3cc9549ab5346f)

Author	SHA1	Message	Date
Andy Fleming	ab5cda9f88	Remove LBC_CACHE_BASE from 8544 DS ... The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming <afleming@freescale.com>	17 years ago
Kumar Gala	859a86a25c	85xx/86xx: Move to dynamic mgmt of LAWs ... With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>	17 years ago
Kumar Gala	4bcae9c92a	85xx: convert MPC8544 DS over to use new LAW init code ... Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	17 years ago
Kumar Gala	83d40dfd79	85xx: Move LAW init code into C ... Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	17 years ago
wdenk	affae2bff8	Initial revision	23 years ago
wdenk	4a5b6a356a	Initial revision	24 years ago