3 Commits (177f4618ed505dcccfe006b4d4bb6abeca90de9f)

Author	SHA1	Message	Date
Chin Liang See	bdef7876ad	arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1 ... Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>	9 years ago
Marek Vasut	4d74c02724	arm: socfpga: sockit: Use more relaxed DRAM timings ... The currently present DRAM timings generated from GHRD 14.0 did not work on SoCkit rev. D because they were too tight. Load the DRAM timings from GHRD 13.0 which are more relaxed and work with SoCkit rev. D. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>	9 years ago
Marek Vasut	952caa289e	arm: socfpga: Add support for Terasic SoCkit board ... Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>	10 years ago