u-boot

Author SHA1 Message Date

Author	SHA1	Message	Date
Michal Simek	421044b183	doc: ARM: Use the right function name Trivial fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>	10 years ago
Anton staaf	46a6d51c82	cache: add ALLOC_CACHE_ALIGN_BUFFER macro This macro is used to allocate cache line size aligned stack buffers for use with DMA hardware. Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Aneesh V <aneesh@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>	14 years ago
Aneesh V	cba4b1809f	arm: do not force d-cache enable on all boards `c2dd0d4554` added dcache_enable() to board_init_r(). This enables d-cache for all ARM boards. As a result some of the arm boards that are not cache-ready are broken. Revert this change and allow platform code to take the decision on d-cache enabling. Also add some documentation for cache usage in ARM. Signed-off-by: Aneesh V <aneesh@ti.com>	14 years ago

Michal Simek

doc: ARM: Use the right function name

Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Anton staaf

46a6d51c82

cache: add ALLOC_CACHE_ALIGN_BUFFER macro

This macro is used to allocate cache line size aligned stack
buffers for use with DMA hardware.

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Aneesh V <aneesh@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>

Aneesh V

cba4b1809f

arm: do not force d-cache enable on all boards

c2dd0d4554 added dcache_enable()
to board_init_r(). This enables d-cache for all ARM boards.
As a result some of the arm boards that are not cache-ready
are broken. Revert this change and allow platform code to
take the decision on d-cache enabling.

Also add some documentation for cache usage in ARM.

Signed-off-by: Aneesh V <aneesh@ti.com>

3 Commits (3285e6cbcc1b848a99f4113f807812c14ed10dea)