Fix the .dts file USB unit addresses not to duplicate each-other.
Fix the board name string to indicate the vendor is Compulab not NVIDIA.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.
Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
The SPI hardware on Seaboard is too broken to use; it is muxed with the
console UART and requires evil interactions between the SPI and UART
drivers to work even partially. The current code in U-Boot is not
sufficient to make this work correctly; auto boot is aborted due to
corruption in the UART RX channel interrupting it.
Instead, move the environment to eMMC, at the end of the second boot
sector. This should not conflict with any other eMMC usage, irrespective
of whether the board boots from SPI, NAND, or eMMC: if U-Boot is stored
in eMMC, it will be stored well below this location. The kernel only
uses the general area of the eMMC once booted, not the boot sectors.
Boards that are derivatives of Seaboard don't have the muxing issue,
and should/could have a separate U-Boot configuration file that does
enable SPI if desired.
Alternatively, the environment could be stored in NAND flash, but we
currently have no driver for that controller.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Store the environment in eMMC, at the end of the second boot sector.
This should not conflict with any other eMMC usage: U-Boot is stored
well below this location, and the kernel only uses the general area
of the eMMC once booted, not the boot sectors.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Store the environment in eMMC, at the end of the second boot sector.
This should not conflict with any other eMMC usage: U-Boot is stored
well below this location, and the kernel only uses the general area
of the eMMC once booted, not the boot sectors.
Note: This assumes the user plugged the standard 8MB MoviNAND card into
J29/HSMMC/POP. If they didn't, the boot sector layout may be different.
However, use of that particular card is standard practice as far as I
know.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Store the environment in eMMC, at the end of the second boot sector.
This should not conflict with any other eMMC usage: U-Boot is stored
well below this location, and the kernel only uses the general area
of the eMMC once booted, not the boot sectors.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This allows MMC drivers to perform cache flusing on the bufffers
without issue.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a device tree for Ventana; the Seaboard file no longer represents
the HW present on Ventana.
Enable USB on Ventana.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The SMSC95xx series may exist either directly on a main board, or as a USB
to Ethernet dongle. However, dongles containing these chips are very rare.
Hence, remove this config option, except on Harmony where such a chip is
actually present on the board.
The asix option remains, since it's a popular chip, and I actively use a
dongle containing this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Override -march setting for tegra to -march=armv4t for files that are
necessary for low level init on tegra.
The recent change to use -march=armv7-a for armv7 caused a regression
on tegra because tegra starts boot on a arm7tdmi processor before
transferring control to the cortex-a9. While still executing on the
arm7tdmi there are calls to getenv_ulong() and memset() that cause an
illegal instruction exception if compiled for armv7.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Correct this warning seen by Albert:
ap20.c:44:18: warning: array subscript is above array bounds
There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
... to enable USB host support, which enables Ethernet support.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
... to enable USB host support, which enables Ethernet support.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is based on top of:
tegra: add alternate UART1 funcmux entry
tegra: add UART1 on GPU funcmux entry
v2: remove enum change
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
CONFIG_CMD_PING/NFS aren't required for Whistler to boot.
Add some comments.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This implements a useful bootcmd for Tegra. The boot order is:
* If USB enabled, USB storage
* Internal MMC (SD card or eMMC)
* If networking is enabled, BOOTP/TFTP
When booting from USB or MMC, the boot script is assumed to be in
partition 1 (although this may be overridden via the rootpart variable),
both ext2 and FAT filesystems are supported, the boot script may exist
in either / or /boot, and the boot script may be named boot.scr.uimg or
boot.scr.
When booting over the network, it is assumed that boot.scr.uimg exists
on the TFTP server. There is less flexibility here since those setting
up network booting are expected to need less hand-holding.
In all cases, it is expected that the initial file loaded is a U-Boot
image containing a script that will load the kernel, load any required
initrd, load any required DTB, and finally bootm the kernel.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
console isn't used by anything, and the kernel should be set appropriately
by whatever script is booting the kernel, not imposed by the bootloader.
mem might be useful, but the current value is pretty bogus, since it
includes nvmem options that make no sense for an upstream kernel, and
equally should not be required for any downstream kernel. Either way, this
is also best left to the kernel boot script.
smpflag isn't used by anything, and again was probably intended to be a
kernel command-line option better set by the kernel boot script.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:
E1120 motherboard
E1108 CPU board
E1116 PMU board
The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.
Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
(In at least some configurations) Whistler uses UART1 on pingroups
UAA, UAB.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass's proposal to fix this on Seaboard was NAK'd, so I
removed his NS16550 references and added a small delay before
SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes
and saw no corruption (crc's matched) and no spurious comm chars.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun <yorksun@freescale.com>
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun <yorksun@freescale.com>
addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigned long.
Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're
orthogonal.
The only caller of addrmap_phys_to_virt() converts the return value to
a pointer anyway.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Remove some unused default environment variables (memctl_intlv_ctl,
perf_mode, diuregs, dium, and diuerr), update 'tftpflash' variable,
and add videobootargs as a Linux command line variable (so that we can
easily pass video= to the kernel).
Signed-off-by: Timur Tabi <timur@freescale.com>
Remove some unused macros and remove all #undef macros.
The RTL8139 network adapter is not shipped with the board nor commonly
used, so don't define it by default. The E1000 is still defined.
Add 57,600 baud as an option. For some reason, this baud rate is missing
from many boards.
Signed-off-by: Timur Tabi <timur@freescale.com>
During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.
Avoid updating these register.They will be programmed during NAND RAMBOOT.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG).
So define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.
Please refer doc/README.mpc85xx for more information
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.
As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.
1) While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction from the debug exception vector (IVPR + IVOR15); since now
we are in AS=0, the application needs to ensure the proper TLB configuration to
have (IVOR + IVOR15) accessible from AS=0 also.
Create a temporary TLB in AS0 to make sure debug exception verctor is
accessible on debug exception.
2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always.
Where MSR = Machine State register
Make sure of MSR[DE] bit is set uniformaly across the different execution
address space i.e. AS0 and AS1.
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
This describes requirement of e500 and e500v2 processor to support external
debugger.
It also provide an insight of the configuration switch required and their
description.
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
On p1010rdb some signals are muxed for tdm/can/uart/flash.
If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" explicitly,
defaultly we keep spi chip selection to spi-flash instead of to
tdm/slic and disable uart1 when not using flexcan, as well disable sdhc.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC
is an integrated device that targets Femto base station market. It combines
Power Architecture e500v2 and DSP StarCore SC3850 core technologies with
MAPLE-B2F baseband acceleration processing elements
BSC9131RDB Overview
-----------------
-1Gbyte DDR3 (on board DDR)
-128Mbyte 2K page size NAND Flash
-256 Kbit M24256 I2C EEPROM
-128 Mbit SPI Flash memory
-USB-ULPI
-eTSEC1: Connected to RGMII PHY
-eTSEC2: Connected to RGMII PHY
-DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.
This patch adds support for mainly Power side functionalities and peripherals
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- BSC9130 is exactly same as BSC9131 except that the max e500v2
core and DSP core frequencies are 800M(these are 1G in case of 9131).
- BSC9231 is similar to BSC9131 except no MAPLE
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
This patch takes care of code pertaining to power side functionality only.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Stephen Warren
Tom Warren
Tom Warren
amartin@nvidia.com
Simon Glass
Lucas Stach
York Sun
Timur Tabi
Shengzhou Liu
Prabhakar Kushwaha