4 Commits (640957042d8f878d093f37aadc04f6d08a7252a1)

Author	SHA1	Message	Date
Stephen Warren	f35cb12511	ARM: tegra: error check Tegra210 XUSB padctl waits ... Add code to detect timeouts when waiting for HW events such as PLL lock done. Any errors are logged and trigger an error return code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>	9 years ago
Stephen Warren	4e4b5574fb	ARM: tegra: add lane tables to Tegra210 XUSB padctl ... Add the tables defining which pads and mux options exist in the Tegra210 XUSB padctl hardware. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>	9 years ago
Stephen Warren	7a908c7e01	ARM: tegra: switch Tegra210 to common XUSB padctl ... This change simply deletes code from the Tegra210 XUSB padctl driver that is already present in the common XUSB padctl code. Since all the arrays in tegra210_socdata are empty, this update may leave the Tegra210 XUSB padctl driver non-functional at run-time. However, (a) this driver is not used yet so no regression can be observed and (b) the next commit will immediately fix this up. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>	9 years ago
Tom Warren	6c43f6c8d9	ARM: Tegra210: Add SoC code/include files for T210 ... All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>	10 years ago