When initializing the core clocks, stick external memory into self-refresh.
This gains us a few cool things:
- support suspend-to-RAM with Linux
- reprogram clocks automatically when doing "go" on u-boot.bin in RAM
- make sure settings are stable before flashing new version
- finally fully unify initialize startup code path between LDR/non-LDR
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some newer Blackfins (like the BF51x) do not have an on-chip voltage
regulator, so do not attempt to program the memory as if it does.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If the board config does not specify an explicit EBIU_SDBCTL value, set it
up with sane values based on other configuration options.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Workaround anomaly 432:
The bfrom_SysControl() firmware function does not clear the SIC_IWR1
register before executing the PLL programming sequence. Therefore, any
interrupt enabled in the SIC_IWR1 register prior to the call to
bfrom_SysControl() can prematurely terminate the idle sequence required
for the PLL to relock properly. SIC_IWR0 is properly handled.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Boot ROM uses EVT1 as the entry point so set that rather than having
to use a tiny jump block in the default EVT1 location.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Looks like the initcode updates fell out of order during my merges. The
patch that really fixes up this code is part of power-on overhaul and so
is too large for merging at this point. Instead, we can disable the code
as no currently in-tree board depends on it. The next merge window will
fix things up properly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Previously, booting over the UART required the baud rate to be known ahead
of time. Using a bit of tricky simple math, we can calculate the new board
rate based on the old divisors.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Newer Blackfin boot roms support using the fast SPI read command rather than
just the slow one. If the functionality is available, then use it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some bits of the DDR MMRs should not be set. If they do, bad things may
happen (like random failures or hardware destruction).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Newer Blackfin's have an on-chip rom with a syscontrol() function that needs
to be used to properly program the memory and voltage settings as it will
include (possibly critical) factory tested bias values.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
As pointed out by Ivan Koryakovskiy, the initialization code was not
actually respecting the CONFIG_CLKIN_HALF option when configuring the
PLL_CTL register.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
All of the duplicated code for Blackfin processors and boot modes have been
unified. After all, the core is the same for all processors, just the
peripheral set differs (which gets handled in the drivers).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger