cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.
Remove the unneeded definition.
Cc: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
novena uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.
Remove the unneeded definition.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Marek Vasut <marex@denx.de>
imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Cc: Martin Donnelly <martin.donnelly@ge.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Heiko Schocher <hs@denx.de>
imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Currently it's recommended to move some configuration options to the
defconfig file.
Move some USB related options to the defconfig file.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
This commit adds support for the Toradex Computer on Modules
Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence
can be easily supported by one board. The board code detects RAM
size at runtime which is one of the differences between the two
boards. The board also uses the UART's in DTE mode, hence making
use of the new DTE support via serial DM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
It's not necessary to use the is_cpu_type function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Added removal of the fsl,ext-reset-output property in the wdog node for board
revisions that pre-date the addition of the external watchdog reset signal.
This property is a recent addition to mainline linux kernel in order to
specify that the IMX watchdog external reset should be used instead of the
internal chip-level reset.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Re-factor the board-specific dt fixups so that they are easier to follow
and extend in the future:
- use defines for DT paths
- use switch/case per board
- order models numerically
There is no functional change in the code
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The hwconfig env var allows user to control hardware specific configuration
of board specific features but not all Ventana boards have the same features.
We will use the magic default value of "_UNKNOWN_" to signify that the
bootloader should create this based on detected board model.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3b1f681131 caused a regression that removes
board info dispaly for Gateworks Ventana boards because it made the invalid
assumption that CONFIG_DISPLAY_BOARDINFO_LATE was the same thing as
CONFIG_DISPLAY_BOARDINFO.
Ventana needs to call show_board_info in late init because we need to have
the i2c eeprom based model info. Re-define CONFIG_DISPLAY_BOARDINFO_LATE
to allow that to happen.
Cc: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The IMX6 PCIe host controller does not have a proper reset and as such there
are several issues that can arise if PCI is enabled in the bootloader follwed
by Linux trying to re-configure LTSSM and/or toggling PERST# to the devices.
For now, the best approach seems to default to disabling PCI by defaulting
pciedisable=1. This can be overridden by the user if they need PCI in the
bootloader, for example:
- GW552x needing ethernet access in bootloader
- GW16082 expansion board needing a device-tree fixup for irq mapping
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Ventana boards with a PCI Marvell Sky2 GigE MAC require the MAC address to
be placed in a DT node in order for the mainline linux driver to obtain it.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW16082 mini-PCI expansion mezzanine uses a TI XIO2001 PCIe-to-PCI
bridge with legacy INTA/B/C/D interrupts. These interrupts are assigned
in the reverse order according to the PCI spec.
If the TI bridge is found on the Ventana PCI bus, add device-tree nodes
according to bus enumeration explicitly defining the interrupt mapping
to override the default PCI mapping in the Linux kernel. This allows
the GW16082 to work with upstream kernels that support device-tree
irq parsing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
There is no need for introducing MX7_SEC, as there is the
CONFIG_ARMV7_BOOT_SEC_DEFAULT option for this purpose.
Switch to CONFIG_ARMV7_BOOT_SEC_DEFAULT and get rid of
MX7_SEC.
Tested by booting a 4.1.15 NXP kernel with mx7dsabresd_secure_defconfig
target.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
USB gadget configuration is set in defconfig and
must be removed from pico-imx6ul.h.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
After moving CONFIG_USB_EHCI_MX7 to Kconfig,
the flag must be set in defconfig for mx7dsabresd.
It is already for the not secure config, it is
missing in the secure configuration.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
It's no need to speed 10 seconds to wait the mmc device out from busy
status. 500 milliseconds enough.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Many SoCs allow power to be applied to or removed from portions of the SoC
(power domains). This may be used to save power. This API provides the
means to control such power management hardware.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix up the call in mmc_load_image_raw_partition() to use the correct
function to obtain the MMC device, so that this code can support driver
model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move zynq to the latest driver model support by enabling CONFIG_DM_MMC,
CONFIG_DM_MMC_OPS and CONFIG_BLK.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is useful information to show how close we are to the limit. At present
it is only available by enabling DEBUG in board_r.c.
Make it available with the 'bdinfo' command also.
Note that this affects ARM only. The bdinfo command is different for each
architecture. Rather than duplicating the code it would be better to
refactor it (as was done with global_data).
Signed-off-by: Simon Glass <sjg@chromium.org>
Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
We currently use dm_scan_fdt_node() to bind devices. It is an internal
function and it requires the caller to know whether we are pre- or post-
relocation.
This requirement has become quite common in drivers, so the current function
is not ideal.
Add a new function with fewer arguments, that does not require internal
headers. This can be used directly as a post_bind() method if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
There are no places to call these functions.
It should be used the callback function.
Then it can be used as static functions.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This e,g is wrong. Maximum/minimum e.g values are swapped each other.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Disable the sun8i emac driver for now, there are 2 issues with it:
1) It is causing issues with network connectivity under the kernel driver,
when booting the kernel with v2 of Corentin's sun8i-h3 emac driver, I get
the connection status bouncing between connected at 100mbps full-duplex
and being down every second.
The second issue is that when trying to use it from u-boot
I get a number of unaligned cache flush errors:
=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c90, 7bf59e10]
CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In sun8i_emac_board_setup, the driver partially configures the syscon
register for H3 EPHY. However, the settings are incomplete, and
completely unusable. The correct settings are later set in
sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists.
It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not
have a 25 MHz clock the EPHY can use.
This patch removes the setting of the syscon register in board_setup,
and also moves set_syscon above mdio_init. While mdio_init does not
access the PHY, it is better to have the PHY parameters setup before
the MDIO bus is registered.
Fixes: a29710c525 ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The sun8i_emac driver erroneously configures the AHB2 clock when it
assumes it is configuring the AXI gates, which is not even documented
or ever appeared in either the WiP kernel driver or Allwinner's original
driver.
As a result, AHB2 clock mux is set to an invalid setting, making the
EPHY unusable.
Fixes: a29710c525 ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diego Dorta
Fabio Estevam
Breno Lima
Stefan Agner
Tim Harvey
Stefano Babic
Tom Rini
Xu Ziyuan
Stephen Warren
Simon Glass
Jaehoon Chung
Hans de Goede
Masahiro Yamada
Chen-Yu Tsai