The PCIe root-complex/endpoint setup as configured via the "pcie_mode"
environment variable will now get passed to the Linux kernel by setting
the device_type property of the PCIe device tree node. For normal root-
complex configuration it will keep its defaults value of "pci" and for
endpoint configuration it will get changed to "pci-endpoint".
Signed-off-by: Stefan Roese <sr@denx.de>
Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds endpoint support for the AMCC Kilauea eval board. It can
be tested by connecting a reworked PCIe cable (only 1x lane singles
connected) to another root-complex.
In this test setup, a 64MB inbound window is configured at BAR0 which maps
to 0 on the PLB side. So accessing this BAR0 from the root-complex will
access the first 64MB of the SDRAM on the PPC side.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.
This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:
pcie_mode=RP:EP:EP
This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.
Per default Yucca will be configured as:
pcie_mode=RP:EP:EP
Per default Katmai will be configured as:
pcie_mode=RP:RP:REP
Per default Kilauea will be configured as:
pcie_mode=RP:RP
Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
(3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access
the SDR registers of the PCIe ports. This makes the overall design
clearer, since it removed a lot of switch statements which are not
needed anymore.
Also, the functions ppc4xx_init_pcie_rootport() and
ppc4xx_init_pcie_entport() are merged into a single function
ppc4xx_init_pcie_port(), since most of the code was duplicated.
This makes maintainance and porting to other 4xx platforms
easier.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(2) This patch renames the functions from 440spe_ to 4xx_ with a
little additional cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(1) This patch renames the files from 440spe_pcie to 4xx_pcie
Signed-off-by: Stefan Roese <sr@denx.de>
Convert using fixup mechanism to suppressing MCK for the duration of config
read/write transaction: while fixups work fine with the case of a precise
exception, we identified a major drawback with this approach when there's
an imprecise case. In this scenario there is the following race condition:
the fixup is (by design) set to catch the instruction following the one
actually causing the exception; if an interrupt (e.g. decrementer) happens
between those two instructions, the ISR code is executed before the fixup
handler the machine check is no longer protected by the fixup handler as it
appears as within the ISR code. In consequence the fixup approach is being
phased out and replaced with explicit suppressing of MCK during a PCIe
config read/write cycle.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
During config transactions on the PCIe bus an attempt to scan for a
non-existent device can lead to a machine check exception with certain
peripheral devices. In order to avoid crashing in such scenarios the
instrumented versions of the config cycle read routines are introduced, so
the exceptions fixups framework can gracefully recover.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Rafal Jaworowski <raj@semihalf.com>
Stefan Roese
Grzegorz Bernacki
Rafal Jaworowski