The 7610 and related parts have an L2IP bit in the L2CR that is
monitored to signal when the L2 cache invalidate is complete whereas the
7450 and related parts utilize L2I for this purpose. However, the
current code does not account for this difference. Additionally the 86xx
L2 cache invalidate code used an "andi" instruction where an "andis"
instruction should have been used.
This patch addresses both of these bugs.
Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
Acked-By: Jon Loeliger <jdl@freescale.com>
Increase number of network RX buffers (PKTBUFSRX in
"include/net.h") for EEPRO100 based boards (especially SP8240)
which showed "Receiver is not ready" errors when U-Boot was
processing the receive buffers slower than the network controller
was filling them.
* Get rid of obsolete include/mpc74xx.h
Wheatley Travis
wdenk