u-boot

Commit Graph

Author	SHA1	Message	Date
Chin Liang See	b38c1d2f6b	arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1 Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>	8 years ago
Marek Vasut	4ae6cfe332	arm: socfpga: mcvevk: Update DRAM clock to 400MHz The MCV SoM has DDR3-1600 DRAMs on it, update the DRAM speed to 400MHz to make use of these DRAMs completely. Signed-off-by: Marek Vasut <marex@denx.de>	10 years ago
Marek Vasut	d88995a82b	arm: socfpga: Add support for DENX MCV SoM and MCVEVK board Add support for DENX MCV SoM, which is CycloneV based and the associated DENX MCVEVK baseboard. The board can boot from eMMC. Ethernet and USB is supported. Signed-off-by: Marek Vasut <marex@denx.de>	10 years ago

Author

SHA1

Message

Date

Chin Liang See

b38c1d2f6b

arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

8 years ago

Marek Vasut

4ae6cfe332

arm: socfpga: mcvevk: Update DRAM clock to 400MHz

The MCV SoM has DDR3-1600 DRAMs on it, update the DRAM speed
to 400MHz to make use of these DRAMs completely.

Signed-off-by: Marek Vasut <marex@denx.de>

10 years ago

Marek Vasut

d88995a82b

arm: socfpga: Add support for DENX MCV SoM and MCVEVK board

Add support for DENX MCV SoM, which is CycloneV based and the
associated DENX MCVEVK baseboard. The board can boot from eMMC.
Ethernet and USB is supported.

Signed-off-by: Marek Vasut <marex@denx.de>

10 years ago

3 Commits (a2777ecb9d11882dba696035defa35c70dd26733)