6 Commits (ad1cf785853eef60e48053ead4fbb47dad840d55)

Author	SHA1	Message	Date
Wolfgang Denk	1a4596601f	Add GPL-2.0+ SPDX-License-Identifier to source files ... Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>	11 years ago
York Sun	472d546054	Consolidate bool type ... 'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>	12 years ago
Marek Vasut	b89c708bb7	GCC4.6: Squash warnings in lattice.c ... lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument 3 has type 'const char *' lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument 4 has type 'long unsigned int' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>	13 years ago
Wolfgang Denk	fb2d6efbf2	FPGA: constify Lattice FPGA code ... The Lattice code was missed by commit e6a857d "fpga: constify to fix build warning" resulting in such warnings: fpga.c: In function 'fpga_load': fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers from pointer target type fpga.c: In function 'fpga_dump': fpga.c:278: warning: passing argument 2 of 'lattice_dump' discards qualifiers from pointer target type Signed-off-by: Wolfgang Denk <wd@denx.de> cc: Stefano Babic <sbabic@denx.de>	13 years ago
Wolfgang Denk	071bc92330	Coding Style cleanup ... Signed-off-by: Wolfgang Denk <wd@denx.de>	14 years ago
Stefano Babic	3b8ac464f2	FPGA: add support for downloading Lattice bitstream ... The patch adds support to load a Lattice's bitstream image (called VME file) into a Lattice FPGA. The code containing the state machine delivered as part of Lattice's ispVMtools is integrated. The FPGA is programmed using the JTAG interface. The board maintainer must provide accessors to drive the JTAG signals TCK, TMS, TDI and to get the value of the input signal TDO. Signed-off-by: Stefano Babic <sbabic@denx.de>	14 years ago