u-boot

Commit Graph

Author	SHA1	Message	Date
Poonam Aggrwal	273a28ad9e	85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	15 years ago
Poonam Aggrwal	924024c396	85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB. The data being modified was in NOR flash which caused the crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	15 years ago
Poonam Aggrwal	82b7725b6d	ppc/85xx: 32bit DDR changes for P1020/P1011 The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	15 years ago
Kumar Gala	2abbd31da6	ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	15 years ago
Poonam Aggrwal	728ece343e	85xx: Add support for P2020RDB board The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	15 years ago

5 Commits (c0c316569f70055eb7c70864aaa6d48666782600)