u-boot

Author	SHA1	Message	Date
Dave Liu	b4983e16d1	fsl-ddr: use the 1T timing as default configuration For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>	16 years ago
Haiying Wang	dfb49108e4	Pass dimm parameters to populate populate controller options Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>	16 years ago
Kumar Gala	9617c8d49a	FSL DDR: Convert MPC8540ADS to new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	17 years ago
Jon Loeliger	39aa1a7348	FSL DDR: Convert MPC8610HPCD to new DDR code. Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	17 years ago
Kumar Gala	6a8e569293	FSL DDR: Convert MPC8641HPCN to new DDR code. Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	17 years ago