u-boot

Author	SHA1	Message	Date
Kumar Gala	5af0fdd81c	85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>	16 years ago
Jean-Christophe PLAGNIOL-VILLARD	6d0f6bcf33	rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>	17 years ago
Andy Fleming	ab5cda9f88	Remove LBC_CACHE_BASE from 8544 DS The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming <afleming@freescale.com>	17 years ago
Kumar Gala	f69766e4b5	85xx: Add the concept of CFG_CCSRBAR_PHYS When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	17 years ago
Kumar Gala	0f7a3dc95c	85xx: Convert MPC8544 DS to new TLB setup Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	17 years ago