For tracing to work it has to be able to access the microsecond timer
without causing a recursive call to the function entry/exit handlers.
Add attributes to the relevant functions to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Pass '-mcpu=xscale' to the compiler instead of march and mtune. This will cause
gcc to define the __XSCALE__ macro.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
The comment in the low-level initialization function cpu_init_crit() says that
the caches are being disabled, but (oddly) the icache is actually turned on.
This is probably not a good idea prior to relocating code, so this patch turns
it off. Tested on the pxa270.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
This change is only done where needed: some linker
scripts may contain relocation symbols yet remain
unchanged.
__rel_dyn_start and __rel_dyn_end each requires
its own output section; putting them in relocation
sections changes their flags and breaks relocation.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This change is only done where needed: some linker
scripts may contain __image_copy_{start,end} yet
remain unchanged.
Also, __image_copy_end needs its own section; putting
it in relocation sections changes their flags and makes
relocation break.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Discard all .dynsym sections from linker scripts
Remove all __dynsym_start definitions from linker scripts
Remove all __dynsym_start references from the codebase
Note: this touches include/asm-generic/sections.h, which
is not ARM-specific, but actual uses of __dynsym_start
are only in ARM, so this patch can safely go through
the ARM repository.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
move uart soft reset code to common place and call
this function from board code, instead of copy and paste
this code for every board.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
[trini: Fix igep0033 build, remove 'regval' on pcm051]
Signed-off-by: Tom Rini <trini@ti.com>
upcoming support for siemens boards switches mpu pll clk in board
code. So make this configurable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
move rtc32k_enable() to common place so all am33xx boards can use it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
This patch initialises the local variable 'shift' to zero.
The uninitialised local variable 'shift' had garbage value and was
resulting in unwnated results in the functions exynos5_get_mmc_clk()
and exynos4_get_mmc_clk().
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
default run mode. Activating the mode early significantly speeds
up boot process.
Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
Move pinmux configurations for the DA830 SoCs from board file
to the arch tree so that it can be used for all da830 based devices.
Also, avoids duplicate pinmuxing in case of NAND.
Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
auxclk0 and auxclk1 are utilized on some OMAP5 boards.
Define the infrastructure needed for accessing them
without using magic numbers.
Also remove unrelated TPS62361 defines from clocks.h
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
The omap2420H4 was the only mainline omap24xx board. Prior to being
fixed by Jon Hunter in time for v2013.04 it had been functionally broken
for a very long time. Remove this board as there's not been interest in
it in U-Boot for quite a long time.
Signed-off-by: Tom Rini <trini@ti.com>
DRA7 EVM board has the below configuration. Adding the
settings for the same here.
2Gb_1_35V_DDR3L part * 2 on EMIF1
2Gb_1_35V_DDR3L part * 4 on EMIF2
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.
This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The newly introduced function setup_warmreset_time(), called
from within prcm_init(), tries to write to the prm_rsttime
OMAP5 register. The struct member holding this register's
address is however initialized for OMAP5 ES2.0 only. On ES1.0
devices this uninitialized value causes a second (warm) reset
at startup.
Add .prm_rsttime address init to the ES1.0 struct.
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Tom Rini <trini@ti.com>
Patch adds a call of abb_setup() function, and proper registers
definitions needed for ABB setup sequence. ABB is initialized
for MPU voltage domain.
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.
Adaptive Body-Bias ldos are present for some voltage domains
starting with OMAP3630. There are three modes of operation:
* Bypass - the default, it just follows the vdd voltage
* Foward Body-Bias - applies voltage bias to increase transistor
performance at the cost of power. Used to operate safely at high
OPPs.
* Reverse Body-Bias - applies voltage bias to decrease leakage and
save power. Used to save power at lower OPPs.
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
The non-SPL build of U-Boot on Tegra only runs on a single CPU, and
hence there is no need to enable the SCU when running U-Boot. If an
SMP OS is booted, and it needs the SCU enabled, it will enable the SCU
itself. U-Boot doing so is redundant.
The one exception is Tegra20, where an enabled SCU is required for some
aspects of PCIe to work correctly.
Some Tegra SoCs contain CPUs without a software-controlled SCU. In this
case, attempting to turn it on actively causes problems. This is the case
for Tegra114. For example, when running Linux, the first (or at least
some very early) user-space process will trigger the following kernel
message:
Unhandled fault: imprecise external abort (0x406) at 0x00000000
This is typically accompanied by that process receving a fatal signal,
and exiting. Since this process is usually pid 1, this causes total
system boot failure.
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, fleshed out description, ported to upstream chipid APIs]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common. Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx. Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.
Reviewed-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This requires that cpu_is_exynos4/5 should be made available before tzpc_init.
Hence this patch also makes necessary changes to have cpu_info in spl and
invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
tzpc_init is common for all exynos5 boards, hence move it to
armv7/exynos so that all other boards can use it.
Also update the smdk5250 Makefile and config file.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28
starts from RAM, so the vectoring table at 0x0 is not present. Craft
code that will be placed at 0x0 and will redirect interrupt vectoring
to proper location of the U-Boot in RAM.
Signed-off-by: Marek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
This patch adds generic codes to support Freescale's Vybrid VF610 CPU.
It aligns Vybrid VF610 platform with i.MX platform. As there are
some differences between VF610 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/vf610 directory.
Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Replace all relocate_code routines from ARM start.S files
with a single instance in file arch/arm/lib/relocate.S.
For PXA, this requires moving the dcache unlocking code
from within relocate_code into c_runtime_cpu_setup.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
cpu_init_crit() can be skipped, but the code is still enabled requiring a
platform to supply lowlevel_init().
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Make U-Boot aware of the Tegra20 SKU 7, and treat it identically
to any other Tegra20.
My Whistler board has a SoC with this SKU.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Make U-Boot aware of the Tegra114 SKU 1, and treat it identically
to any other Tegra114.
This value is used on (at least some) Dalmore boards with a production
rather than engineering chip. Such boards are in the hands of some
partners who want to use upstream U-Boot.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
When adjusting peripheral clocks always use find_best_divider()
instead of clk_get_divider() even when a secondary divider is not
available. In the case where is requested clock is too slow to be
derived from the parent clock this allows a best effort to get close
to the requested clock.
This comes up for commands like "sf" where the user can pass a clock
speed on the command line or "sspi" where the clock is hardcoded to
1MHz, but the Tegra114 SPI controller can't go that low.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
While other architectures have enabled these gcc / ld options for some
time on U-Boot itself, ARM has only been doing this on SPL. Enable this
on full U-Boot as well now.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add sama5d3xek support with following feature
- boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector
- boot from SPI flash support
- boot from SD card support
- LCD support
- EMAC support
- USB OHCI support
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add support for following features:
- nand boot, with PMECC 2bit ECC for 512 bytes sector
- SPI flash boot
- SD card boot
- LCD support
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[fix -Wimplicit-function-declaration for at91_lcd_hw_init()]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The boot parameters passed from SPL to UBOOT
must be saved as a part of uboot's gd data
as early as possible, before we will inadvertently
overwrite it. So adding a arch_cpu_init for the required
Socs to save it.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
The boot parameters are read from individual variables
assigned for each of them. This been corrected and now
they are stored as a part of the global data 'gd'
structure. So read them from 'gd' instead.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
Currently save_boot_params saves the boot parameters passed
from romcode. But this is not stored in a writable location
consistently. So the current code would not work for a
'XIP' boot. Change this by saving the boot parameters in
'gd' which is always writable. Also add a 'C' function
instead of an assembly code that is more readable.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Simon Glass
Mike Dunn
Albert ARIBAUD
Heiko Schocher
Amar
Sergey Yanovich
Vishwanathrao Badarkhe, Manish
Lubomir Popov
Tom Rini
Sricharan R
Lokesh Vutla
Nishanth Menon
Andrii Tseglytskyi
Tom Warren
Inderpal Singh
Marek Vasut
Alison Wang
Axel Lin
Stephen Warren
Allen Martin
Akshay Saraswat
Bo Shen
Wu, Josh