callback function should be moved into sdhci_ops struct.
Other controller can use these ops for controlling clock or their own
specific register.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
This code is used for only pic32_sdhci controller.
To remove the "#ifdef", moves to pic32_sdhci.c.
And use the get_cd callback function.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Buswidth is depeneded on Hardware schematic.
Evne though host can support the 8bit buswidth, if hardware doesn't
support 8bit mode, it doesn't work fine.
So the buswidth mode selection leaves a matter in each SoC drivers.
On the contrary to this, hardware supports 8bit mode, but host doesn't
support it. then controller has to disable the MMC_MODE_8BIT.
(Host can check whether 8bit mode is supported or not, since V3.0)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
While I moved the options, I also renamed them so that they are all
prefixed with MMC_SDHCI_.
This commit was created in the following steps.
[1] Rename with the following command
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_MMC_SDMA/CONFIG_MMC_SDHCI_SDMA/g
s/CONFIG_BCM2835_SDHCI/CONFIG_MMC_SDHCI_BCM2835/g
s/CONFIG_KONA_SDHCI/CONFIG_MMC_SDHCI_KONA/g
s/CONFIG_MV_SDHCI/CONFIG_MMC_SDHCI_MV/g
s/CONFIG_S5P_SDHCI/CONFIG_MMC_SDHCI_S5P/g
s/CONFIG_SPEAR_SDHCI/CONFIG_MMC_SDHCI_SPEAR/g
'
[2] create the Kconfig entries in drivers/mmc/Kconfig
[3] Move the options by the following command
tools/moveconfig.py -y MMC_SDHCI_SDMA MMC_SDHCI_BCM2835 \
MMC_SDHCI_KONA MMC_SDHCI_MV MMC_SDHCI_S5P MMC_SDHCI_SPEAR
[4] Sort drivers/mmc/Makefile for readability
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This pathc is fixed the below thing.
If misaligned the cache range, Just flush to CACHLINE_SIZE.
"CACHE: Misaligned operation at range [7ae55b00, 7ae55b08]"
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Use the generic error number instead of meaningless value.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
"host->version" isn't a SoC specific value.
It doesn't need to get in each SoC drivers.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
No need for per-SoC adjustment for this parameter. It should be
determined by the slowest hardware. Currently, no board overrides
this CONFIG, so 3.2 sec is large enough. (If not, we can make it
even larger.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This CONFIG is not configurable since it is not guarded by #ifndef.
Nobody has complained about that, so there is no need to keep it as
a CONFIG option.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_BLK is enabled, add_sdhci() is never called. Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_BLK is enabled, add_sdhci() is never called. Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
"Hardware doesn't specify base clock frequency" may not be only the
error case of sdhci_setup_cfg(). It is better to print this where
the corresponding error is triggered.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_BLK is enabled, add_sdhci() is never called.
So, sdhci_reset() is not called, either. This is a problem for
my board as it needs the reset to start from a sane state.
Move the add_sdhci() call to sdhci_init(), which is visited
by both of the with/without CONFIG_BLK cases.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
When disabled CONFIG_MMC_SDMA, variable caps didn't use.
This patch fixes the compiler error for -Wunused-but-set-variable
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Some arguments don't need to pass to sdhci_setup_cfg.
Generic variable can be used in sdhci_setup_cfg, and some arguments are
already included in sdhci_host struct.
It's enough that just pass the board specific things to sdhci_setup_cfg().
After removing the unnecessary arguments, it's more simpler than before.
It doesn't consider "Version" and "Capabilities" anymore in each SoC
driver.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
buswidth isn't used anywhere in sdhci_setup_cfg.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This "commit 429790026021d522d51617217d4b86218cca5750" is wrong.
SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit.
For example, Exynos didn't have CTRL_HISPD. But Highspeed mode
is supported.
(This quirks doesn't mean that driver didn't support the Highseepd mode.)
Note: If driver didn't support the Highspeed Mode, use or add the other
quirks.
After applied this patch, all Exynos SoCs are just running with 25MHz.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Use the generic error number instead of specific error number.
If use the generic error number, it can debug more easier.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
There is no data, it doesn't needs to wait for completing data transfer.
(It seems that it can be removed.)
Almost all timeout error is occured from stop command without data.
After applied this patch, I hope that we don't need to increase timeout value anymore.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
The current timeout detection logic is not very nice; it calls
get_timer(start) in the while() loop, and then calls it again after
the loop to check if a timeout error happened.
Because of the time difference between the two calls of get_timer(),
the timeout detected after the loop may not be true.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Disable internal clock by clearing the internal
clock enable bit. This bit needs to be cleared too
when we stop the SDCLK for changing the frequency
divisor. This bit should be set to zero when the
device is not using the Host controller.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Otherwise, ocassionally see errors like this:
Flashing sparse image at offset 2078720
Flashing Sparse Image
sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
write_sparse_image: Write failed, block #2181088 [0]
This does not affect the actual writing speed, which is controlled by
the default value:
CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT
It only increases the retries when reading:
SDHCI_INT_STATUS
to avoid the timeout error.
Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
This is a device number, and we want to use 'dev' to mean a driver model
device. Rename the member.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.
Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Clear high speed bit if it was not supported by
the driver.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Emil Lenchak <emill@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
According to the SDHC specification, stopping the SD Clock is by setting
the SD Clock Enable bit in the Clock Control register at 0, instead of
setting all bits at 0.
Before stopping the SD clock, we need to make sure all SD transactions
to complete, so add checking the CMD and DAT bits in the Presen State
register, before stopping the SD clock.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
following problem occured. The SPL runs in internal SRAM which is
the L2 cache locked to memory. When the MMC buffers now are located
on the stack (or bss), the SDIO controller (SDHCI) can't write into
this L2 cache memory.
This patch introduces a method to use a fixed buffer that will be
used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
This way, the board can use this buffer address located in SDRAM
for all transfers. This solves this SPL problem on the A38x and
should only be used in the SPL U-Boot version.
Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Timeout interrupt also work for response busy command(R1b) like
cmd38/cmd6. So need to set it accordingly. Current code only
set timeout for data command.
Signed-off-by: Kevin Liu <kliu5@marvell.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
SDHCI_HOST_CONTROL is a byte-sized register, so don't write to it
as if it were a long, as that would result in clobbering the three
registers following.
Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
Fix bus width switching from 8-bit mode down to 4-bit or 1-bit modes on
Samsung SoCs using SDHCI_QUIRK_USE_WIDE8. These SoCs report controller
version 2.0 yet they support 8-bit bus widths. If 8-bit mode was
previously enabled and then an operation like "mmc dev" caused a switch
back down to 4-bit or 1-bit mode, WIDE8 was left set, causing failures.
This problem was manifested by "mmc dev" timing out.
Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
The way that struct mmc was implemented was a bit of a mess;
configuration and internal state all jumbled up in a single structure.
On top of that the way initialization is done with mmc_register leads
to a lot of duplicated code in drivers.
Typically the initialization got something like this in every driver.
struct mmc *mmc = malloc(sizeof(struct mmc));
memset(mmc, 0, sizeof(struct mmc);
/* fill in fields of mmc struct */
/* store private data pointer */
mmc_register(mmc);
By using the new mmc_create call one just passes an mmc config struct
and an optional private data pointer like this:
struct mmc = mmc_create(&cfg, priv);
All in tree drivers have been updated to the new form, and expect
mmc_register to go away before long.
Changes since v1:
* Use calloc instead of manually calling memset.
* Mark mmc_register as deprecated.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Using an array is pointless; even more pointless (and scary) is using
sprintf to fill it without a format string.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Remove the in-structure ops and put them in mmc_ops with
a constant pointer to it.
This makes the mmc structure smaller as well as conserving
code space (in theory).
All in-tree drivers are converted as well; this is done in a
single patch in order to not break git bisect.
Changes since V1:
Fix compilation b0rked issue on omap platforms where OMAP_GPIO was
not set.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Fixup prints to show where the print is done from, and
a few minor formatting/grammar issues.
Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Old command timeout value was too small and it caused I/O errors which
led to uncompleted read/write/erase operations and filesystem errors.
Timeout adaptation fixes this issue.
Changes in sdhci_send_command() function:
- change timeout variable to static
- increase default command timeout to 100 ms
- add definition of max command timeout value,
which can be redefined in each board config file
- wait for card ready state for max defined time
if it doesn't exceed defined maximum or return COMM_ERR
Once successfully increased timeout value will be used in next function
call. This fix was tested on Goni, Trats, Trats2 boards by testing UMS
on MMC storage.
Changes v2:
- move global variable cmd_timeout into function sdhci_send_command()
- change condition "==" to ">=" when comparing time with timeout
- print information about timeout increasing and card busy timeout
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
The patch fixes the improper read and write of sdhci
host control register for sdma transfer.
The problem comes when reading and writing 1 byte long
host control register with the sdhci_readl() and
sdhci_writel(). The misuse of these functions overwrite
the value of the next registers which are in 4 bytes boundary.
This patch replaces four byte register read/write functions
with one byte read/write ones. Beside, it eliminates
unnecessary bit operation. i.e. or-ing zero against a variable.
Signed-off-by: Juhyun (Justin) Oh <Juhyun_Oh@sigmadesigns.com>
Samsung SoC is supported the WIDE8, even if Controller version is v2.0.
So add the SDHCI_QUIRK_USE_WIDE8 for Samsung-SoC.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Jaehoon Chung
Masahiro Yamada
Wenyou Yang
Siva Durga Prasad Paladugu
Simon Glass
Steve Rae
Andrei Pistirica
Stefan Roese
Kevin Liu
Rob Herring
Matt Reimer
Jeroen Hofstee
Pantelis Antoniou
Darwin Rambo
Przemyslaw Marczak
Juhyun \(Justin\) Oh
Wolfgang Denk